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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2012-08-17drm/i915: fix hsw uncached pteDaniel Vetter
2012-07-20drm/i915: fix up PCH backlight #define mixupDaniel Vetter
2012-07-20drm/i915: Add comments to explain the BSD tail write workaroundChris Wilson
2012-07-20drm/i915/context: Add missing IVB context sizesBen Widawsky
2012-07-20drm/i915/context/: s/CTX/CXTBen Widawsky
2012-07-05drm/i915: program FDI_RX TP and FDI delaysEugeni Dodonov
2012-07-05drm/i915: adjust framebuffer base address on gen4+Daniel Vetter
2012-07-05drm/i915: introduce crtc->dspaddr_offsetDaniel Vetter
2012-07-05drm/i915: fix PIPE_DDI_PORT_MASKPaulo Zanoni
2012-07-05drm/i915: enable RC6 workaround on HaswellEugeni Dodonov
2012-07-05drm/i915: add RPS configuration for HaswellEugeni Dodonov
2012-07-03drm/i915: support Haswell force wakingEugeni Dodonov
2012-07-03drm/i915: Implement w/a for sporadic read failures on waking from rc6Chris Wilson
2012-06-28drm/i915: fix PIPE_WM_LINETIME definitionPaulo Zanoni
2012-06-25Merge tag 'v3.5-rc4' into drm-intel-next-queuedDaniel Vetter
2012-06-20drm/i915: enable display messages to GT on ValleyViewJesse Barnes
2012-06-20drm/i915: add HDMI and DP port enumeration on ValleyViewJesse Barnes
2012-06-20drm/i915: Enable DP panel power sequencing for ValleyViewShobhit Kumar
2012-06-20drm/i915: ValleyView mode setting limits and PLL functionsJesse Barnes
2012-06-18drm/i915: add L3 bank clock gating disable on VLVJesse Barnes
2012-06-18drm/i915: add TDL unit clock gating disable for VLVJesse Barnes
2012-06-18drm/i915: disable RCBP and VDS unit clock gating on SNB and VLVJesse Barnes
2012-06-14drm/i915: PIPE_CONTROL_TLB_INVALIDATEBen Widawsky
2012-06-14drm/i915: Ivybridge MI_ARB_ON_OFF context w/aBen Widawsky
2012-06-14drm/i915: CXT_SIZE register offsets addedBen Widawsky
2012-06-12drm/i915: clear up backlight #define confusion on gen4+Daniel Vetter
2012-06-12drm/i915: pnv has a backlight polarity control bit, tooDaniel Vetter
2012-06-06drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handlerAdam Jackson
2012-06-05drm/i915: fix up ivb plane 3 pageflipsDaniel Vetter
2012-05-31drm/i915: remap l3 on hw initBen Widawsky
2012-05-31drm/i915: Dynamic Parity Detection handlingBen Widawsky
2012-05-30drm/i915: explicitly disable the DIPs we're not usingPaulo Zanoni
2012-05-21drm/i915: SDVO hotplug have different interrupt status bits for i915/i965/g4xChris Wilson
2012-05-21drm/i915: Inspect the right status bits for DP/HDMI hotplug on gen4Chris Wilson
2012-05-20drm/i915: implement hsw_write_infoframePaulo Zanoni
2012-05-19drm/i915: add new Haswell DIP controls registersEugeni Dodonov
2012-05-08drm/i915: set the DIP port on ibx_write_infoframePaulo Zanoni
2012-05-08drm/i915: mask the video DIP frequency when changing itPaulo Zanoni
2012-05-08drm/i915: mask the video DIP port selectPaulo Zanoni
2012-05-08drm/i915: DSL_LINEMASK is 12 bits only on gen2Paulo Zanoni
2012-05-06drm/i915: Support pageflipping interrupts for all 3-pipes on IVBChris Wilson
2012-05-05drm/i915: also reset the media engine on gen4/5Daniel Vetter
2012-05-03drm/i915: use the new masked bit macro some moreDaniel Vetter
2012-05-03drm/i915: create macros to handle masked bitsDaniel Vetter
2012-05-03drm/i915: manage PCH PLLs separately from pipesJesse Barnes
2012-04-18drm/i915: [GEN7] Use HW scheduler for fixed function shadersBen Widawsky
2012-04-18drm/i915: Replace open coded MI_BATCH_GTTChris Wilson
2012-04-17drm/i915: Mask reserved bits in display/sprite address registersArmin Reese
2012-04-17drm/i915: add WRPLL divider programming bitsEugeni Dodonov
2012-04-17drm/i915: add definition of LPT FDI port width registersEugeni Dodonov
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