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12 daysirqchip/irq-realtek-rtl: Add multicore supportMarkus Stockhausen
The Realtek interrupt driver currently supports only single core systems. So the higher end devices like RTL839x and RTL930x with dual VPEs must be driven with NR_CPU=1. Enhance the driver to support multicore (dual VPE) systems. For this: - Extend the register map for multiple cores - Search for multiple CPU cores in the devicetree - Improve the register helpers to support multiple cores - Add an affinity setter - Enhance the IRQ handler for multiple cores Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260604182506.1113440-3-markus.stockhausen@gmx.de
12 daysirqchip/irq-realtek-rtl: Add/simplify register helpersMarkus Stockhausen
The Realtek interrupt controller has two important registers that are used by the driver in several places - GIMR: global interrupt mask register - IRR: Interrupt routing registers The usage of these registers is very inconsistent. GIMR is addressed directly while IRR has a helper that needs a macro as an input. Harmonize this by providing consistent helpers that improve code readability. The callers of these helpers use classic lock/unlock functions and sometimes use the wrong locking helper. E.g. irqsave variants are used in mask/unmask although not needed. Adapt and fix the surrounding call locations. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260604182506.1113440-2-markus.stockhausen@gmx.de
13 daysirqchip/loongarch-ir: Add IR (interrupt redirection) irqchip supportTianyang Zhang
The main function of the redirect interrupt controller is to manage the redirected-interrupt table, which consists of many redirected entries. When MSI interrupts are requested, the driver creates a corresponding redirected entry that describes the target CPU/vector number and the operating mode of the interrupt. The redirected interrupt module has an independent cache, and during the interrupt routing process, it will prioritize the redirected entries that hit the cache. The irqchip driver can invalidate certain entry caches via a command queue. Co-developed-by: Liupu Wang <wangliupu@loongson.cn> Signed-off-by: Liupu Wang <wangliupu@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260513012839.2856463-5-zhangtianyang@loongson.cn
13 daysirqchip/loongarch-avec: Return IRQ_SET_MASK_OK_DONE when keep affinityTianyang Zhang
Interrupt redirection support requires a new redirect domain, which will appear as a child domain of avecintc domain. For each interrupt source, avecintc domain only provides the CPU/interrupt vectors, while redirect domain provides other operations to synchronize the interrupt affinity information among multiple cores. When modifying the affinity of an interrupt associated with the redirect domain, if the avecintc domain detects that the actual interrupt affinity hasn't been changed, then the redirect domain doesn't need to perform any operations. To achieve the above purpose, in avecintc_set_affinity() when the current affinity remains valid, then return value is set to IRQ_SET_MASK_OK_DONE. This doesn't introduce any compatibility issues, even if the new return value causing msi_domain_set_affinity() to no longer perform the call to irq_chip_write_msi_msg(): 1) When both avecintc and redirect exist in the system, the msg_address and msg_data no longer change after the allocation phase, so it does not actually require updating the MSI message info. 2) When only avecintc exists in the system, the irq_domain_activate_irq() interface will be responsible for the initial configuration of the MSI message info, which is unconditional. After that, if unnecessary, there is no modification to the MSI message info. Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260513012839.2856463-4-zhangtianyang@loongson.cn
13 daysirqchip/loongarch-avec: Prepare for interrupt redirection supportTianyang Zhang
Interrupt redirection support requires a new interrupt chip, which needs to share data structures, constants and functions with the AVECINTC code. So move them to the header file and make the required functions public. Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20260513012839.2856463-3-zhangtianyang@loongson.cn
13 daysirqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit positionMukesh Ojha
The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit represents one PDC pin. The bank index and bit position within the bank are encoded in the flat pin number as bits [31:5] and [4:0] respectively. Replace the open-coded division and modulo with FIELD_GET() and GENMASK() to make the bit extraction self-documenting and consistent with the FIELD_PREP() style already used in the PDC_VERSION() macro. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-5-mukesh.ojha@oss.qualcomm.com
13 daysirqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register fieldsMukesh Ojha
The PDC hardware version register encodes major, minor and step fields in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively. The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200) with no indication of this encoding. Add GENMASK-based field definitions for each sub-field and a PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making the encoding self-documenting. Replace the magic constant with PDC_VERSION(3, 2, 0). Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-4-mukesh.ojha@oss.qualcomm.com
13 daysirqchip/qcom-pdc: Tighten ioremap clamp to single DRV region sizeMukesh Ojha
The QCOM_PDC_SIZE constant (0x30000) was introduced to work around old sm8150 DTs that described a too-small PDC register region, causing the driver to silently expand the ioremap to cover three DRV regions. Now that the preceding DT fixes have corrected all platforms to describe only the APSS DRV region (0x10000), the oversized clamp is no longer needed. Replace QCOM_PDC_SIZE with PDC_DRV_SIZE (0x10000) in the clamp so the minimum mapped size matches a single DRV region. The clamp and warning are intentionally kept to preserve backward compatibility with any old DTs that may still describe a smaller region. While at it, rename PDC_DRV_OFFSET to PDC_DRV_SIZE since the constant represents the size of a DRV region and is used as both the ioremap minimum size and the offset to the previous DRV region. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-3-mukesh.ojha@oss.qualcomm.com
13 daysirqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpersMukesh Ojha
The __pdc_enable_intr() function contains a version branch that selects between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for HW >= 3.2. These two paths share no code and serve different hardware. Split them into two focused static functions: pdc_enable_intr_bank() for HW < 3.2 and pdc_enable_intr_cfg() for HW >= 3.2. No functional change. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com
13 daysirqchip/exynos-combiner: Remove useless spinlockMarek Szyprowski
irq_controller_lock doesn't protect anything, it is a leftover from early development or copy/paste. Remove it completely. Fixes: 96031b31a4b3 ("irqchip/exynos-combiner: Switch to raw_spinlock") Suggested-by: Thomas Gleixner <tglx@kernel.org> Suggested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/all/20260521090453.bbUZ00tS@linutronix.de Link: https://patch.msgid.link/20260522061012.2687122-1-m.szyprowski@samsung.com/
13 daysirqchip/renesas-rzt2h: Add error interrupts supportCosmin Tanislav
The Renesas RZ/T2H ICU is able to report errors for CA55, GIC, and various IPs. Unmask these errors, request the IRQs and report them when they occur. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260520203117.1516442-4-cosmin-gabriel.tanislav.xa@renesas.com
13 daysirqchip/renesas-rzt2h: Add software-triggered interrupts supportCosmin Tanislav
The Renesas RZ/T2H ICU supports software-triggerable interrupts. Add a dedicated rzt2h_icu_intcpu_chip irq_chip which implements rzt2h_icu_intcpu_set_irqchip_state() to allow injecting these interrupts. Request the INTCPU IRQs when IRQ injection is enabled to report them when they occur. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260520203117.1516442-3-cosmin-gabriel.tanislav.xa@renesas.com
13 daysMerge branch 'irq/urgent' into irq/driversThomas Gleixner
Pick up fixes so subsequent changes apply.
2026-05-26irqchip/gic-v4: Don't advertise VLPIs if no ITS is probedMostafa Saleh
When accidentally setting “kvm-arm.vgic_v4_enable=1” on a system that has no MSI controller device tree node and GICv4, it results a panic as “gic_domain” is NULL and the kernel attempts to access it. Unable to handle kernel NULL pointer dereference at virtual address 0000000000000028 Mem abort info: ESR = 0x0000000096000006 CPU: 1 UID: 0 PID: 295 Comm: lkvm-static Not tainted 7.1.0-rc4-ge3f15ad3970e #5 PREEMPT Hardware name: linux,dummy-virt (DT) pstate: 81402005 (Nzcv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : __irq_domain_instantiate+0x1d4/0x578 lr : __irq_domain_instantiate+0x1cc/0x578 Set vLPI support to false at init time if the host has no ITS, so it propagates properly to kvm_vgic_global_state.has_gicv4. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mostafa Saleh <smostafa@google.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260526125317.3672297-1-smostafa@google.com
2026-05-21irqchip/renesas-rzt2h: Use pm_runtime_put_sync() in probe error pathCosmin Tanislav
pm_runtime_put() may trigger the idle check after pm_runtime_disable() is run as part of devm_pm_runtime_enable()'s cleanup action, leaving runtime PM active. Use pm_runtime_put_sync() to ensure the idle check runs synchronously. Fixes: 13e7b3305b64 ("irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver") Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260520203117.1516442-2-cosmin-gabriel.tanislav.xa@renesas.com
2026-05-21irqchip/exynos-combiner: Switch to raw_spinlockMarek Szyprowski
The exynos-combiner driver uses a regular spinlock to protect access to the combiner interrupt status register in combiner_handle_cascade_irq(), which is invoked in hard interrupt context as a chained interrupt handler. When PREEMPT_RT is enabled on ARM, regular spinlock is converted to a sleeping lock (mutex-based), which must not be used in atomic context such as hard interrupt handlers. Switch the irq_controller_lock to raw_spinlock, which remains a true non-sleeping spinlock even under PREEMPT_RT. Fixes: a900e5d99718 ("ARM: exynos: move exynos4210-combiner to drivers/irqchip") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org>
2026-05-11irqchip/gic-v3-its: Use FIELD_MODIFY()Hans Zhang
Use FIELD_MODIFY() to remove open-coded bit manipulation. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260430162954.44156-1-18255117159@163.com
2026-05-11irqchip/econet-en751221: Support MIPS 34Kc VEIC modeCaleb James DeLisle
The Vectored External Interrupt Controller mode present in the MIPS 34Kc and 1004Kc variants causes the CPU to stop dispatching interrupts by the normal code path and instead it sends those interrupts to the external interrupt controller to be prioritized, renumbered, and sent back. When they come back, they are handled through a different path using a dispatch table, so plat_irq_dispatch() never sees action. This of course subverts the traditional intc hierarchy, and on the 1004Kc the interrupt controller is standardized (IRQ_GIC) so it can be reasonably considered part of the CPU itself - and tighter coupling between IRQ_GIC and arch/mips/* is tolerable. However on the 34Kc the intc is defined by each SoC vendor, so it's required to have a modular driver - but for a device which in fact ends up taking over the entire interrupt system. Let the DT describe which IRQs which come from the CPU and should be routed back and handled by the CPU intc. These particularly include the two IPI interrupts which would otherwise necessitate duplication of all the IPI supporting infrastructure from the CPU intc. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260430164157.6026-3-cjd@cjdns.fr
2026-05-11irqchip/riscv-imsic: Clear interrupt move state during CPU offliningYong-Xuan Wang
Affinity changes of IMSIC interrupts have to be careful to not lose an interrupt in the process. Each vector keeps track of an affinity change in progress with two pointers in struct imsic_vector. imsic_vector::move_prev points to the previous CPU target data and imsic_vector::move_next to the designated new CPU target data. imsic_vector::move_prev on the new CPU can only be cleared after the previous CPU has cleared imsic_vector::move_next, which ususally happens in __imsic_remote_sync(). In case of CPU hot-unplug __imsic_remote_sync() is not invoked because the CPU is already marked offline. That means imsic_vector::move_prev becomes stale until the CPU is onlined again. The stale pointer prevents further affinity changes for the affected interrupts. Solve this by clearing the imsic_vector::move_prev pointers in the CPU hotplug offline path. [ tglx: Replace word salad in change log ] Fixes: 0f67911e821c ("irqchip/riscv-imsic: Separate next and previous pointers in IMSIC vector") Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260508-imsic-v2-1-e9f08dd46cf5@sifive.com
2026-05-11irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type()Xianwei Zhao
meson_s4_gpio_irq_set_type() uses the both-edge trigger register for configuring level type and single edge mode interrupts, which is not correct. Use REG_EDGE_POL instead. Fixes: bbd6fcc76b39 ("irqchip: Add support for Amlogic A4 and A5 SoCs") Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com
2026-05-11irqchip/meson-gpio: Add support for Amlogic A9 SoCsXianwei Zhao
The Amlogic A9 SoCs supports the following GPIO interrupt lines: A9 IRQ Number: - 95:86 10 pins on bank Y - 85:84 2 pins on bank CC - 83:64 20 pins on bank A - 63:48 16 pins on bank Z - 47:30 18 pins on bank X - 29:22 8 pins on bank H - 21:14 8 pins on bank M - 13:0 14 pins on bank B A9 AO IRQ Number: - 38 1 pins on bank TESTN - 37:31 7 pins on bank C - 30:13 18 pins on bank D - 12:0 13 pins on bank AO Update the driver to handle these variants. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-3-9dc5f3e022e0@amlogic.com
2026-05-11Merge branch 'irq/urgent' into irq/driversThomas Gleixner
to synchronize upstream fixes on which other changes depend on.
2026-05-11irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type()Xianwei Zhao
meson_s4_gpio_irq_set_type() uses the both-edge trigger register for configuring level type and single edge mode interrupts, which is not correct. Use REG_EDGE_POL instead. Fixes: bbd6fcc76b39 ("irqchip: Add support for Amlogic A4 and A5 SoCs") Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com
2026-05-11irqchip/ath79-cpu: Remove unused functionRosen Penev
ath79_cpu_irq_init() was part of the legacy pre-OF code that got removed a while back. Remove it to get rid of a missing prototype warning, reported by the kernel test robot. [ tglx: Fix the subject prefix. Sigh ... ] Fixes: 51fa4f8912c0 ("MIPS: ath79: drop legacy IRQ code") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Rosen Penev <rosenp@gmail.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260506085522.1210143-1-rosenp@gmail.com Closes: https://lore.kernel.org/oe-kbuild-all/202412011509.kGQkDr1y-lkp@intel.com/
2026-05-11irqchip/gic-v5: Allocate ITS parent LPIs as a rangeSascha Bischoff
The ITS MSI domain no longer manages LPI allocation directly. LPIs are allocated and freed by the parent LPI domain, which can now handle a full range of interrupts and unwind partial allocations internally. Make the ITS domain request and release the parent IRQs as a single range instead of iterating over each interrupt. The ITS allocation path then only needs to reserve EventIDs, allocate the parent range, and fill in the ITS irq_data for each MSI. Since no operation in the per-MSI loop can fail, the partial parent-free unwind becomes unnecessary. On teardown, reset the ITS irq_data for the range and then release the parent range in one call, leaving LPI teardown to the LPI domain. Fixes: 0f0101325876 ("irqchip/gic-v5: Add GICv5 LPI/IPI support") Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260506093634.382062-4-sascha.bischoff@arm.com
2026-05-11irqchip/gic-v5: Support range allocation for LPIsSascha Bischoff
The per-IPI parent allocation loop returns immediately on failure and leaks any parent interrupts allocated by earlier iterations. The GICv5 LPI domain now owns LPI allocation and teardown internally, but its irq_domain callbacks still reject requests where nr_irqs is greater than one. This forces child domains to allocate and free LPIs one at a time even when the interrupt core requests a contiguous range. Handle multi-interrupt allocation and teardown in the LPI domain by iterating over the requested range and unwinding any partially allocated state on failure. Allocate the parent LPIs for the IPI domain with a single range request as well, which cures the leakage problem. Fixes: 0f0101325876 ("irqchip/gic-v5: Add GICv5 LPI/IPI support") Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260506093634.382062-3-sascha.bischoff@arm.com
2026-05-11irqchip/gic-v5: Move LPI allocation into the LPI domainSascha Bischoff
The IPI and ITS MSI domains currently allocate and release LPIs directly, then pass the selected LPI ID to the parent LPI domain. This leaks the LPI domain's allocation policy into its child domains and forces each child to duplicate part of the parent domain's teardown. Make the LPI domain allocate LPIs in its .alloc() callback and release them in a matching .free() callback. Child domains can then request a parent interrupt without passing an implementation-specific LPI ID, and the LPI lifetime is tied to the domain that owns the LPI namespace. Remove the gicv5_alloc_lpi() and gicv5_free_lpi() wrappers now that no external caller needs to manage LPIs directly. This is a preparatory change for an actual leakage problem in the allocation code and therefore tagged with the same Fixes tag. Fixes: 0f0101325876 ("irqchip/gic-v5: Add GICv5 LPI/IPI support") Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260506093634.382062-2-sascha.bischoff@arm.com
2026-05-06irqchip/starfive: Fix error check for devm_platform_ioremap_resource()Chen Ni
devm_platform_ioremap_resource() returns an error pointer on failure, not NULL. Fix the check to use IS_ERR() and return PTR_ERR() to correctly handle allocation failures. Fixes: 2f59ca185497 ("irqchip/starfive: Use devm_ interfaces to simplify resource release") Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://patch.msgid.link/20260506041413.1670799-1-nichen@iscas.ac.cn
2026-04-30irqchip/qcom: Unify user-visible "Qualcomm" nameKrzysztof Kozlowski
Various names for Qualcomm as a company are used in user-visible config options: QCOM, Qualcomm and Qualcomm Technologies. Switch to unified "Qualcomm" so it will be easier for users to identify the options when for example running menuconfig. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260427070121.18422-2-krzysztof.kozlowski@oss.qualcomm.com
2026-04-30irqchip/starfive: Implement irq_set_type() and irq_ack() callbacksChanghuang Liang
Add irq_set_type() callback to support configuring interrupt trigger types (level high/low, edge rising/falling) for the JHB100 interrupt controller. Also add irq_ack() callback as required by handle_edge_irq(). Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260416064751.632138-6-changhuang.liang@starfivetech.com
2026-04-30irqchip/starfive: Increase the interrupt source number up to 64Mason Huo
StarFive JHB100 SoC interrupt controller actually supports 64 interrupt sources, the original code only supported up to 32. now it is extended to 64. Also use guard(raw_spinlock) to automatically release spinlocks. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260416064751.632138-5-changhuang.liang@starfivetech.com
2026-04-30irqchip/starfive: Use devm_ interfaces to simplify resource releaseChanghuang Liang
Use devm_ interfaces to simplify resource release. Make clock and reset get optional as they are not used on the JHB100 SoC. Replace pr_ logging with dev_* logging. Use __free(kfree) cleanup attribute to auto-free irqc on error paths Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260416064751.632138-4-changhuang.liang@starfivetech.com
2026-04-30irqchip/starfive: Rename jh8100 to jhb100Changhuang Liang
The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the driver file, Kconfig symbol, and internal references from "jh8100" to "jhb100" to accurately reflect the supported hardware. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260416064751.632138-3-changhuang.liang@starfivetech.com
2026-04-30irqchip/aspeed-intc: Remove AST2700-A0 supportRyan Chen
The existing AST2700 interrupt controller driver ("aspeed,ast2700-intc-ic") was written against the A0 pre-production design. From A1 onwards (retained in the A2 production silicon), the interrupt fabric was re-architected: interrupt routing is programmable and interrupt outputs can be directed to multiple upstream controllers (PSP GIC, Secondary Service Processor (SSP) NVIC, Tertiary Service Processor (TSP) NVIC, and Boot MCU interrupt controller). This design requires route resolution and a controller hierarchy model which the A0 driver cannot represent. Remove driver support for A0 in favour of the driver for the A2 production design. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260407-irqchip-v5-4-c0b0a300a057@aspeedtech.com
2026-04-30irqchip/ast2700-intc: Add KUnit tests for route resolutionRyan Chen
Add a KUnit suite for aspeed_intc0_resolve_route(). Cover invalid arguments, invalid domain/range data, connected and disconnected mappings, and malformed upstream range cases. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260407-irqchip-v5-3-c0b0a300a057@aspeedtech.com
2026-04-30irqchip/ast2700-intc: Add AST2700-A2 supportRyan Chen
The AST2700 interrupt fabric is shared by multiple integrated processors (PSP/SSP/TSP/BootMCU), each with its own interrupt controller and its own devicetree view of the system. As a result, interrupt routing cannot be treated as fixed: the valid route for a peripheral interrupt depends on which processor is consuming it. The INTC0 driver models this by creating a hierarchical irqdomain under the upstream interrupt controller selected by the interrupt-parent property in the devicetree. Information derived from this relationship is incorporated into the route resolution logic for the controller. The INTC1 driver implements the banked INTM-fed controller and forwards interrupts toward INTC0, without embedding assumptions about the final destination processor. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260407-irqchip-v5-2-c0b0a300a057@aspeedtech.com
2026-04-17Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm updates from Paolo Bonzini: "Arm: - Add support for tracing in the standalone EL2 hypervisor code, which should help both debugging and performance analysis. This uses the new infrastructure for 'remote' trace buffers that can be exposed by non-kernel entities such as firmware, and which came through the tracing tree - Add support for GICv5 Per Processor Interrupts (PPIs), as the starting point for supporting the new GIC architecture in KVM - Finally add support for pKVM protected guests, where pages are unmapped from the host as they are faulted into the guest and can be shared back from the guest using pKVM hypercalls. Protected guests are created using a new machine type identifier. As the elusive guestmem has not yet delivered on its promises, anonymous memory is also supported This is only a first step towards full isolation from the host; for example, the CPU register state and DMA accesses are not yet isolated. Because this does not really yet bring fully what it promises, it is hidden behind CONFIG_ARM_PKVM_GUEST + 'kvm-arm.mode=protected', and also triggers TAINT_USER when a VM is created. Caveat emptor - Rework the dreaded user_mem_abort() function to make it more maintainable, reducing the amount of state being exposed to the various helpers and rendering a substantial amount of state immutable - Expand the Stage-2 page table dumper to support NV shadow page tables on a per-VM basis - Tidy up the pKVM PSCI proxy code to be slightly less hard to follow - Fix both SPE and TRBE in non-VHE configurations so that they do not generate spurious, out of context table walks that ultimately lead to very bad HW lockups - A small set of patches fixing the Stage-2 MMU freeing in error cases - Tighten-up accepted SMC immediate value to be only #0 for host SMCCC calls - The usual cleanups and other selftest churn LoongArch: - Use CSR_CRMD_PLV for kvm_arch_vcpu_in_kernel() - Add DMSINTC irqchip in kernel support RISC-V: - Fix steal time shared memory alignment checks - Fix vector context allocation leak - Fix array out-of-bounds in pmu_ctr_read() and pmu_fw_ctr_read_hi() - Fix double-free of sdata in kvm_pmu_clear_snapshot_area() - Fix integer overflow in kvm_pmu_validate_counter_mask() - Fix shift-out-of-bounds in make_xfence_request() - Fix lost write protection on huge pages during dirty logging - Split huge pages during fault handling for dirty logging - Skip CSR restore if VCPU is reloaded on the same core - Implement kvm_arch_has_default_irqchip() for KVM selftests - Factored-out ISA checks into separate sources - Added hideleg to struct kvm_vcpu_config - Factored-out VCPU config into separate sources - Support configuration of per-VM HGATP mode from KVM user space s390: - Support for ESA (31-bit) guests inside nested hypervisors - Remove restriction on memslot alignment, which is not needed anymore with the new gmap code - Fix LPSW/E to update the bear (which of course is the breaking event address register) x86: - Shut up various UBSAN warnings on reading module parameter before they were initialized - Don't zero-allocate page tables that are used for splitting hugepages in the TDP MMU, as KVM is guaranteed to set all SPTEs in the page table and thus write all bytes - As an optimization, bail early when trying to unsync 4KiB mappings if the target gfn can just be mapped with a 2MiB hugepage x86 generic: - Copy single-chunk MMIO write values into struct kvm_vcpu (more precisely struct kvm_mmio_fragment) to fix use-after-free stack bugs where KVM would dereference stack pointer after an exit to userspace - Clean up and comment the emulated MMIO code to try to make it easier to maintain (not necessarily "easy", but "easier") - Move VMXON+VMXOFF and EFER.SVME toggling out of KVM (not *all* of VMX and SVM enabling) as it is needed for trusted I/O - Advertise support for AVX512 Bit Matrix Multiply (BMM) instructions - Immediately fail the build if a required #define is missing in one of KVM's headers that is included multiple times - Reject SET_GUEST_DEBUG with -EBUSY if there's an already injected exception, mostly to prevent syzkaller from abusing the uAPI to trigger WARNs, but also because it can help prevent userspace from unintentionally crashing the VM - Exempt SMM from CPUID faulting on Intel, as per the spec - Misc hardening and cleanup changes x86 (AMD): - Fix and optimize IRQ window inhibit handling for AVIC; make it per-vCPU so that KVM doesn't prematurely re-enable AVIC if multiple vCPUs have to-be-injected IRQs - Clean up and optimize the OSVW handling, avoiding a bug in which KVM would overwrite state when enabling virtualization on multiple CPUs in parallel. This should not be a problem because OSVW should usually be the same for all CPUs - Drop a WARN in KVM_MEMORY_ENCRYPT_REG_REGION where KVM complains about a "too large" size based purely on user input - Clean up and harden the pinning code for KVM_MEMORY_ENCRYPT_REG_REGION - Disallow synchronizing a VMSA of an already-launched/encrypted vCPU, as doing so for an SNP guest will crash the host due to an RMP violation page fault - Overhaul KVM's APIs for detecting SEV+ guests so that VM-scoped queries are required to hold kvm->lock, and enforce it by lockdep. Fix various bugs where sev_guest() was not ensured to be stable for the whole duration of a function or ioctl - Convert a pile of kvm->lock SEV code to guard() - Play nicer with userspace that does not enable KVM_CAP_EXCEPTION_PAYLOAD, for which KVM needs to set CR2 and DR6 as a response to ioctls such as KVM_GET_VCPU_EVENTS (even if the payload would end up in EXITINFO2 rather than CR2, for example). Only set CR2 and DR6 when consumption of the payload is imminent, but on the other hand force delivery of the payload in all paths where userspace retrieves CR2 or DR6 - Use vcpu->arch.cr2 when updating vmcb12's CR2 on nested #VMEXIT instead of vmcb02->save.cr2. The value is out of sync after a save/restore or after a #PF is injected into L2 - Fix a class of nSVM bugs where some fields written by the CPU are not synchronized from vmcb02 to cached vmcb12 after VMRUN, and so are not up-to-date when saved by KVM_GET_NESTED_STATE - Fix a class of bugs where the ordering between KVM_SET_NESTED_STATE and KVM_SET_{S}REGS could cause vmcb02 to be incorrectly initialized after save+restore - Add a variety of missing nSVM consistency checks - Fix several bugs where KVM failed to correctly update VMCB fields on nested #VMEXIT - Fix several bugs where KVM failed to correctly synthesize #UD or #GP for SVM-related instructions - Add support for save+restore of virtualized LBRs (on SVM) - Refactor various helpers and macros to improve clarity and (hopefully) make the code easier to maintain - Aggressively sanitize fields when copying from vmcb12, to guard against unintentionally allowing L1 to utilize yet-to-be-defined features - Fix several bugs where KVM botched rAX legality checks when emulating SVM instructions. There are remaining issues in that KVM doesn't handle size prefix overrides for 64-bit guests - Fail emulation of VMRUN/VMLOAD/VMSAVE if mapping vmcb12 fails instead of somewhat arbitrarily synthesizing #GP (i.e. don't double down on AMD's architectural but sketchy behavior of generating #GP for "unsupported" addresses) - Cache all used vmcb12 fields to further harden against TOCTOU bugs x86 (Intel): - Drop obsolete branch hint prefixes from the VMX instruction macros - Use ASM_INPUT_RM() in __vmcs_writel() to coerce clang into using a register input when appropriate - Code cleanups guest_memfd: - Don't mark guest_memfd folios as accessed, as guest_memfd doesn't support reclaim, the memory is unevictable, and there is no storage to write back to LoongArch selftests: - Add KVM PMU test cases s390 selftests: - Enable more memory selftests x86 selftests: - Add support for Hygon CPUs in KVM selftests - Fix a bug in the MSR test where it would get false failures on AMD/Hygon CPUs with exactly one of RDPID or RDTSCP - Add an MADV_COLLAPSE testcase for guest_memfd as a regression test for a bug where the kernel would attempt to collapse guest_memfd folios against KVM's will" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (373 commits) KVM: x86: use inlines instead of macros for is_sev_*guest x86/virt: Treat SVM as unsupported when running as an SEV+ guest KVM: SEV: Goto an existing error label if charging misc_cg for an ASID fails KVM: SVM: Move lock-protected allocation of SEV ASID into a separate helper KVM: SEV: use mutex guard in snp_handle_guest_req() KVM: SEV: use mutex guard in sev_mem_enc_unregister_region() KVM: SEV: use mutex guard in sev_mem_enc_ioctl() KVM: SEV: use mutex guard in snp_launch_update() KVM: SEV: Assert that kvm->lock is held when querying SEV+ support KVM: SEV: Document that checking for SEV+ guests when reclaiming memory is "safe" KVM: SEV: Hide "struct kvm_sev_info" behind CONFIG_KVM_AMD_SEV=y KVM: SEV: WARN on unhandled VM type when initializing VM KVM: LoongArch: selftests: Add PMU overflow interrupt test KVM: LoongArch: selftests: Add basic PMU event counting test KVM: LoongArch: selftests: Add cpucfg read/write helpers LoongArch: KVM: Add DMSINTC inject msi to vCPU LoongArch: KVM: Add DMSINTC device support LoongArch: KVM: Make vcpu_is_preempted() as a macro rather than function LoongArch: KVM: Move host CSR_GSTAT save and restore in context switch LoongArch: KVM: Move host CSR_EENTRY save and restore in context switch ...
2026-04-14Merge tag 'irq-msi-2026-04-12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull MSI interrupt update from Thomas Gleixner: "A small update for the MSI interrupt library to check for callers which fail to provide the mandatory irq_write_msi_msg() callback, which prevents a NULL pointer dereference later" * tag 'irq-msi-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/msi-lib: Refuse initialization when irq_write_msi_msg() is missing
2026-04-14Merge tag 'irq-drivers-2026-04-12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull interrupt chip driver updates from Thomas Gleixner: - A large refactoring for the Renesas RZV2H driver to add new interrupt types cleanly - A large refactoring for the Renesas RZG2L driver to add support the new RZ/G3L variant - Add support for the new NXP S32N79 chip in the IMX irq-steer driver - Add support for the Apple AICv3 variant - Enhance the Loongson PCH LPC driver so it can be used on MIPS with device tree firmware - Allow the PIC32 EVIC driver to be built independent of MIPS in compile tests - The usual small fixes and enhancements all over the place * tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits) irqchip/irq-pic32-evic: Add __maybe_unused for board_bind_eic_interrupt in COMPILE_TEST irqchip/renesas-rzv2h: Kill icu_err string irqchip/renesas-rzv2h: Kill swint_names[] irqchip/renesas-rzv2h: Kill swint_idx[] irqchip/renesas-rzg2l: Add NMI support irqchip/renesas-rzg2l: Clear the shared interrupt bit in rzg2l_irqc_free() irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in rzg2l_irq_set_type() irqchip/gic-v3: Print a warning for out-of-range interrupt numbers irqchip/renesas-rzg2l: Add shared interrupt support irqchip/renesas-rzg2l: Add RZ/G3L support irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro irqchip/renesas-rzg2l: Dynamically allocate fwspec array irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ and TINT handlers irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ and TINT helpers irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with TINT-specific handlers irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and TINT functions irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functions irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances ...
2026-04-13Merge tag 'kvmarm-7.1' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 updates for 7.1 * New features: - Add support for tracing in the standalone EL2 hypervisor code, which should help both debugging and performance analysis. This comes with a full infrastructure for 'remote' trace buffers that can be exposed by non-kernel entities such as firmware. - Add support for GICv5 Per Processor Interrupts (PPIs), as the starting point for supporting the new GIC architecture in KVM. - Finally add support for pKVM protected guests, with anonymous memory being used as a backing store. About time! * Improvements and bug fixes: - Rework the dreaded user_mem_abort() function to make it more maintainable, reducing the amount of state being exposed to the various helpers and rendering a substantial amount of state immutable. - Expand the Stage-2 page table dumper to support NV shadow page tables on a per-VM basis. - Tidy up the pKVM PSCI proxy code to be slightly less hard to follow. - Fix both SPE and TRBE in non-VHE configurations so that they do not generate spurious, out of context table walks that ultimately lead to very bad HW lockups. - A small set of patches fixing the Stage-2 MMU freeing in error cases. - Tighten-up accepted SMC immediate value to be only #0 for host SMCCC calls. - The usual cleanups and other selftest churn.
2026-04-07irqchip/irq-pic32-evic: Add __maybe_unused for board_bind_eic_interrupt in ↵Brian Masney
COMPILE_TEST There are a few ifdefs in this driver so that it can be compiled on all architectures when COMPILE_TEST is set. board_bind_eic_interrupt is defined in arch/mips/ for normal usage, however when this driver is compiled with COMPILE_TEST on other architectures, it is defined as a static variable inside this driver. This causes the following warning: drivers/irqchip/irq-pic32-evic.c:54:15: warning: variable 'board_bind_eic_interrupt' set but not used [-Wunused-but-set-global] 54 | static void (*board_bind_eic_interrupt)(int irq, int regset); | ^ Annotate the static variable with __maybe_unused to avoid having to put even more ifdefs into this driver. Fixes: 282f8b547d51d ("irqchip/irq-pic32-evic: Define board_bind_eic_interrupt for !MIPS builds") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260403-irq-pic32-evic-unused-v1-1-447cdc0675ec@redhat.com Closes: https://lore.kernel.org/oe-kbuild-all/202603300715.4HuMMAFb-lkp@intel.com/
2026-04-07irqchip/renesas-rzv2h: Kill icu_err stringGeert Uytterhoeven
Replace the string variable icu_err by its expanded value where needed, to improve readability. This reduces generated code size by 16 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/c7472bec20dea2c4d63e390e8e293b7d7003ef39.1775205874.git.geert+renesas@glider.be
2026-04-07irqchip/renesas-rzv2h: Kill swint_names[]Geert Uytterhoeven
The array swint_names[] just contains expansions of "int-ca55-%u". Replace it by formatting the strings where needed, to improve readability. Despite the two error messages can no longer be shared with the ICU error cases, this reduces generated code size by 56 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/aceab3fbc307ef428dfd62d8d846b68704dea012.1775205874.git.geert+renesas@glider.be
2026-04-07irqchip/renesas-rzv2h: Kill swint_idx[]Geert Uytterhoeven
The array swint_idx[] just contains an identity mapping. Replace it by using the index directly, to simplify the code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/0f32ba2a4701311710d02ff4fa2fd472b56745c4.1775205874.git.geert+renesas@glider.be
2026-04-01irqchip/renesas-rzg2l: Add NMI supportBiju Das
The RZ/G2L SoC has an NMI interrupt. Add support for the NMI interrupt. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260401114504.332825-1-biju.das.jz@bp.renesas.com
2026-03-31irqchip/renesas-rzg2l: Clear the shared interrupt bit in rzg2l_irqc_free()Biju Das
rzg2l_irqc_free() invokes irq_domain_free_irqs_common(), which internally calls irq_domain_reset_irq_data(). That explicitly sets irq_data->hwirq to 0. Consequently, irqd_to_hwirq(d) returns 0 when called after it. Since 0 falls outside the valid shared IRQ ranges, rzg2l_irqc_is_shared_and_get_irq_num() evaluates to false, completely bypassing the test_and_clear_bit() operation. This leaves the bit set in priv->used_irqs, causing future allocations to fail with -EBUSY. Fix this by retrieving irq_data and caching hwirq before calling irq_domain_free_irqs_common(). Fixes: e0fcae27ff57 ("irqchip/renesas-rzg2l: Add shared interrupt support") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260328103324.134131-2-biju.das.jz@bp.renesas.com
2026-03-31irqchip/riscv-aplic: Restrict genpd notifier to device tree onlyJessica Liu
On ACPI systems, the aplic's pm_domain is set to acpi_general_pm_domain, which provides its own power management callbacks (e.g., runtime_suspend via acpi_subsys_runtime_suspend). aplic_pm_add() unconditionally calls dev_pm_genpd_add_notifier() when dev->pm_domain is non‑NULL, leading to a comparison between runtime_suspend and genpd_runtime_suspend. This results in the following errors when ACPI is enabled: riscv-aplic RSCV0002:00: failed to create APLIC context riscv-aplic RSCV0002:00: error -ENODEV: failed to setup APLIC in MSI mode Fix this by checking for dev->of_node before adding or removing the genpd notifier, ensuring it is only used for device tree based systems. Fixes: 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC states across suspend/resume") Signed-off-by: Jessica Liu <liu.xuemei1@zte.com.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260331093029749vRpdH-0qoEqjS0Wnn9M4x@zte.com.cn
2026-03-29Merge tag 'irq-urgent-2026-03-29' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Ingo Molnar: - Fix TX completion signaling bug in the Qualcomm MPM irqchip driver - Fix probe error handling in the Renesas RZ/V2H(P) irqchip driver * tag 'irq-urgent-2026-03-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/renesas-rzv2h: Fix error path in rzv2h_icu_probe_common() irqchip/qcom-mpm: Add missing mailbox TX done acknowledgment
2026-03-28irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in ↵Biju Das
rzg2l_irq_set_type() Simplify the locking logic in rzg2l_irq_set_type() by using guard(), eliminating the need for an explicit unlock call. [ tglx: Remove the pointless cleanup.h include. The spinlock guards come from spinlock.h ] Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260328103324.134131-3-biju.das.jz@bp.renesas.com
2026-03-26irqchip/gic-v3: Print a warning for out-of-range interrupt numbersGeert Uytterhoeven
gic_irq_domain_translate() does not check if an interrupt number lies within the valid range of the specified interrupt type. Add these checks, and print a warning if the interrupt number is out of range. This can help flagging incorrectly described Extended SPI and PPI interrupts in DT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/ce695ea46decc816974179314a86f2b9b5cad6a9.1772799134.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.0.4) at 2026-06-17 01:04:31 +0000