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4 daysMerge tag 'phy-for-7.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Core: - Add suuport for "rx-polarity" and "tx-polarity" device tree properties and phy common properties to manage this New Support: - Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for that. - SpacemiT PCIe/combo PHY and K1 USB2 PHY driver. - HDMI 2.1 FRL configuration support and driver enabling for rockchip samsung-hdptx driver - TI TCAN1046 phy - Renesas RZ/V2H(P) and RZ/V2N usb3 - Mediatek MT8188 hdmi-phy - Google Tensor SoC USB PHY driver - Apple Type-C PHY Updates: - Subsystem conversion for clock round_rate() to determine_rate() - TI USB3 DT schema conversion - Samsung ExynosAutov920 usb3, combo hsphy and ssphy support" * tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits) phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate() dt-bindings: phy: ti,control-phy-otghs: convert to DT schema dt-bindings: phy: ti,phy-usb3: convert to DT schema phy: tegra: xusb: Remove unused powered_on variable phy: renesas: rcar-gen3-usb2: add regulator dependency phy: GOOGLE_USB: add TYPEC dependency phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable() phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC dt-bindings: phy: renesas,usb2-phy: Document mux-states property dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config phy: rockchip: samsung-hdptx: Drop hw_rate driver data phy: rockchip: samsung-hdptx: Compute clk rate from PLL config phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists ...
2026-01-21phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL supportCristian Ciocaltea
The PHY is capable of handling four HDMI 2.1 Fixed Rate Link (FRL) lanes, and each one can operate at any of the rates of 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps. Add the necessary driver changes to support the feature. Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-11-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helperCristian Ciocaltea
In order to facilitate introduction of HDMI 2.1 FRL support and to avoid recomputing the link rate after verifying the HDMI configuration given as input, extend rk_hdptx_phy_verify_hdmi_config() by providing an optional output parameter to store the validated configuration. For improved code readability, also rename the existing hdmi input parameter. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-10-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Switch to driver specific HDMI configCristian Ciocaltea
In preparation to support the FRL operation mode which gets configured via the lanes and rate per lane tuple, switch to a driver specific struct for configuring the link rate and bpc. This simplifies and optimizes the implementation by allowing implicit switches between TMDS and FRL rates, without requiring additional checks of the active PHY mode followed by recalculations of the link rate when operating in FRL mode. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-9-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Drop hw_rate driver dataCristian Ciocaltea
The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep track of the clock rate programmed in hardware and support implementing the ->recalc_rate() callback in hdptx_phy_clk_ops. Computing the clock rate from the actual PHY PLL configuration seems to work reliably, hence remove the now redundant struct member. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-8-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Compute clk rate from PLL configCristian Ciocaltea
Improve ->recalc_rate() callback of hdptx_phy_clk_ops to calculate the initial clock rate based on the actual PHY PLL configuration as retrieved from the related hardware registers. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-7-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq listsCristian Ciocaltea
Drop redundant reg_sequence entries from rk_hdptx_common_cmn_init_seq[], i.e. those that are either duplicated or overridden in rk_hdptx_tmds_cmn_init_seq[]. Additionally, a few items do not really belong to the former, hence move them to the latter. That's mostly a preparatory step for adding FRL support. No functional changes intended at this point. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-6-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Enable lane output in common helperCristian Ciocaltea
In preparation to support FRL mode, move the PHY lane output enablement from the TMDS specific configuration to the common *_post_enable_lane() helper and make sure it gets turned off in *_phy_disable(). Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-5-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixesCristian Ciocaltea
Fix the naming inconsistencies for some of the functions and global variables: * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable * Replace '_ropll_tmds_' with '_tmds_ropll_' globally * Replace 'hdtpx' with 'hdptx' globally Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-4-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Fix coding style alignmentCristian Ciocaltea
Handle a bunch of reported checkpatch.pl complaints: CHECK: Alignment should match open parenthesis Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-3-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-21phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay()Cristian Ciocaltea
rk_hdptx_dp_reset() is allowed to sleep, hence replace the busy waiting with usleep_range(), to allow other threads to run. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-2-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-14phy: rockchip: inno-usb2: Fix a double free bug in rockchip_usb2phy_probe()Wentao Liang
The for_each_available_child_of_node() calls of_node_put() to release child_np in each success loop. After breaking from the loop with the child_np has been released, the code will jump to the put_child label and will call the of_node_put() again if the devm_request_threaded_irq() fails. These cause a double free bug. Fix by returning directly to avoid the duplicate of_node_put(). Fixes: ed2b5a8e6b98 ("phy: phy-rockchip-inno-usb2: support muxed interrupts") Cc: stable@vger.kernel.org Signed-off-by: Wentao Liang <vulab@iscas.ac.cn> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260109154626.2452034-1-vulab@iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: rockchip: usb: Simplify with scoped for each OF child loopKrzysztof Kozlowski
Use scoped for-each loop when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251224124407.208354-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: rockchip: phy-rockchip-samsung-hdptx: convert from round_rate() to ↵Brian Masney
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-8-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-24phy: rockchip: phy-rockchip-inno-hdmi: convert from round_rate() to ↵Brian Masney
determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20251212-phy-clk-round-rate-v3-7-beae3962f767@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip: naneng-combphy: use existing DT property check for rk3528Chukun Pan
The naneng-combphy driver already has DT property checks for "rockchip,enable-ssc" and "rockchip,ext-refclk", use it for the rk3528_combphy_cfg. Also aligned the indentation of the rk3528_combphy_grfcfgs parameters (using tabs). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20250910122000.951100-1-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config tableCristian Ciocaltea
Drop a bunch of unused members from struct ropll_config and make the static ropll_tmds_cfg table more readable: * add a table header * sort rows by rate * convert hex values to decimal (for consistency) Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251221-phy-hdptx-pll-fix-v2-2-ae4abf7f75a1@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz ↵Cristian Ciocaltea
output Attempting to make use of a 1080p@120Hz display mode with 10 bpc RGB on my Acer XV275K P3 monitor results in a blank image. A similar behavior has been reported on Philips 279M1RV. The faulty modeline is created by drm_gtf_mode_complex() based on the following EDID entry from the Standard Timings block: GTF: 1920x1080 119.999987 Hz 16:9 138.840 kHz 368.759000 MHz It's worth noting the computed pixel clock ends up being slightly higher at 368.881000 MHz. Nevertheless, this seems to work consistently fine with 8 bpc RGB. After switching to 10 bpc, the TMDS character rate expected for the mode increases to 461.101250 MHz, as per drm_hdmi_compute_mode_clock(). Since there is no entry for this rate in the ropll_tmds_cfg table, the necessary HDMI PLL configuration parameters are calculated dynamically by rk_hdptx_phy_clk_pll_calc(). However, the resulting output rate is not quite a perfect match, i.e. 461.100000 MHz. That proved to be the actual root cause of the problem. Add a new entry to the TMDS configuration table and provide the necessary frequency division coefficients for the PHY PLL to generate the expected 461.101250 MHz output. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management") Tested-by: Derek Foreman <derek.foreman@collabora.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251221-phy-hdptx-pll-fix-v2-1-ae4abf7f75a1@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip-samsung-dcphy: Discard pm_runtime_put() return valueRafael J. Wysocki
Passing pm_runtime_put() return value to the callers is not particularly useful. Returning an error code from pm_runtime_put() merely means that it has not queued up a work item to check whether or not the device can be suspended and there are many perfectly valid situations in which that can happen, like after writing "on" to the devices' runtime PM "control" attribute in sysfs for one example. It also happens when the kernel is configured with CONFIG_PM unset. Accordingly, update samsung_mipi_dcphy_exit() to simply discard the return value of pm_runtime_put() and always return success to the caller. This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2281919.Icojqenx9y@rafael.j.wysocki Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip: inno-usb2: fix communication disruption in gadget modeLuca Ceresoli
When the OTG USB port is used to power to SoC, configured as peripheral and used in gadget mode, communication stops without notice about 6 seconds after the gadget is configured and enumerated. The problem was observed on a Radxa Rock Pi S board, which can only be powered by the only USB-C connector. That connector is the only one usable in gadget mode. This implies the USB cable is connected from before boot and never disconnects while the kernel runs. The related code flow in the PHY driver code can be summarized as: * the first time chg_detect_work starts (6 seconds after gadget is configured and enumerated) -> rockchip_chg_detect_work(): if chg_state is UNDEFINED: property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); [Y] * rockchip_chg_detect_work() changes state and re-triggers itself a few times until it reaches the DETECTED state: -> rockchip_chg_detect_work(): if chg_state is DETECTED: property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); [Z] At [Y] all existing communications stop. E.g. using a CDC serial gadget, the /dev/tty* devices are still present on both host and device, but no data is transferred anymore. The later call with a 'true' argument at [Z] does not restore it. Due to the lack of documentation, what chg_det.opmode does exactly is not clear, however by code inspection it seems reasonable that is disables something needed to keep the communication working, and testing proves that disabling these lines lets gadget mode keep working. So prevent changes to chg_det.opmode when there is a cable connected (VBUS present). Fixes: 98898f3bc83c ("phy: rockchip-inno-usb2: support otg-port for rk3399") Cc: stable@vger.kernel.org Closes: https://lore.kernel.org/lkml/20250414185458.7767aabc@booty/ Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://patch.msgid.link/20251127-rk3308-fix-usb-gadget-phy-disconnect-v2-2-dac8a02cd2ca@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: rockchip: inno-usb2: fix disconnection in gadget modeLouis Chauvet
When the OTG USB port is used to power the SoC, configured as peripheral and used in gadget mode, there is a disconnection about 6 seconds after the gadget is configured and enumerated. The problem was observed on a Radxa Rock Pi S board, which can only be powered by the only USB-C connector. That connector is the only one usable in gadget mode. This implies the USB cable is connected from before boot and never disconnects while the kernel runs. The problem happens because of the PHY driver code flow, summarized as: * UDC start code (triggered via configfs at any time after boot) -> phy_init -> rockchip_usb2phy_init -> schedule_delayed_work(otg_sm_work [A], 6 sec) -> phy_power_on -> rockchip_usb2phy_power_on -> enable clock -> rockchip_usb2phy_reset * Now the gadget interface is up and running. * 6 seconds later otg_sm_work starts [A] -> rockchip_usb2phy_otg_sm_work(): if (B_IDLE state && VBUS present && ...): schedule_delayed_work(&rport->chg_work [B], 0); * immediately the chg_detect_work starts [B] -> rockchip_chg_detect_work(): if chg_state is UNDEFINED: if (!rport->suspended): rockchip_usb2phy_power_off() <--- [X] At [X], the PHY is powered off, causing a disconnection. This quickly triggers a new connection and following re-enumeration, but any connection that had been established during the 6 seconds is broken. The code already checks for !rport->suspended (which, somewhat counter-intuitively, means the PHY is powered on), so add a guard for VBUS as well to avoid a disconnection when a cable is connected. Fixes: 98898f3bc83c ("phy: rockchip-inno-usb2: support otg-port for rk3399") Cc: stable@vger.kernel.org Closes: https://lore.kernel.org/lkml/20250414185458.7767aabc@booty/ Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com> Co-developed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://patch.msgid.link/20251127-rk3308-fix-usb-gadget-phy-disconnect-v2-1-dac8a02cd2ca@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limitsCristian Ciocaltea
Fixup PHY deskew FIFO to prevent the phase of D2 lane going ahead of other lanes. It's worth noting this might only happen when dealing with HDMI 2.0 rates. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-3-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidthCristian Ciocaltea
Due to its relatively low frequency, a noise stemming from the 24MHz PLL reference clock may traverse the low-pass loop filter of ROPLL, which could potentially generate some HDMI flash artifacts. Reduce ROPLL loop bandwidth in an attempt to mitigate the problem. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-2-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc modeCristian Ciocaltea
When making use of the clock provider functionality, the output clock does normally match the TMDS character rate, which is what the PHY PLL gets configured to. However, this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output_clock_rate = tmds_char_rate * 8 / bpc Since the existence of the clock divider wasn't taken into account when support for high bpc has been introduced, make the necessary adjustments to report the correct clock rate. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management") Reported-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-1-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562Shawn Lin
When PCIe link enters L1 PM substates, the PHY will turn off its PLL for power-saving. However, it turns off the PLL too fast which leads the PHY to be broken. According to the PHY document, we need to delay PLL turnoff time. Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/1763459526-35004-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528Shawn Lin
When PCIe link enters L1 PM substates, the PHY will turn off its PLL for power-saving. However, it turns off the PLL too fast which leads the PHY to be broken. According to the PHY document, we need to delay PLL turnoff time. Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: inno-dsidphy: Add support for rk3506Chaoyi Chen
For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106020632.92-7-kernel@airkyi.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-10-06Merge tag 'phy-for-6.18' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "The usual bunch of device support and update to drivers. New Support - Qualcomm SM8750 QMP PCIe PHY dual lane support, PMIV0104 eusb2 repeater support, QCS8300 eDP PHY support - Renesas RZ/T2H and RZ/N2H support and updates to driver for that - TI TCAN1051 phy support - Rockchip rk3588 dphy support, RK3528 combphy support Updates: - cadence updates for calibration and polling for ready and enabling of lower resolutions, runtime pm support, - Rockchip: enable U3 otg port - Renesas USXGMII mode support - Qualcomm UFS PHY and PLL regulator load support" * tag 'phy-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (64 commits) phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required phy: cadence: cdns-dphy: Enable lower resolutions in dphy phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet phy: renesas: r8a779f0-ether-serdes: add USXGMII mode phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X dt-bindings: phy: Add Sophgo CV1800 USB phy phy: cadence: cdns-dphy: Update calibration wait time for startup state machine phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling phy: renesas: rcar-gen3-usb2: Fix ID check logic with VBUS valid dt-bindings: phy: ti,tcan104x-can: Document TI TCAN1051 phy: lynx-28g: check return value when calling lynx_28g_pll_get phy: qcom: m31-eusb2: Fix the error log while enabling clock phy: rockchip: usbdp: Remove redundant ternary operators phy: renesas: rcar-gen3-usb2: Remove redundant ternary operators phy: hisilicon: Remove redundant ternary operators phy: qcom-qmp-ufs: Add PHY and PLL regulator load ...
2025-09-22phy: rockchip-pcie: switch to FIELD_PREP_WM16 macroNicolas Frattaroli
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. The Rockchip PCIe PHY driver, used on the RK3399, has its own definition of HIWORD_UPDATE. Remove it, and replace instances of it with hw_bitfield.h's FIELD_PREP_WM16. To achieve this, some mask defines are reshuffled, as FIELD_PREP_WM16 uses the mask as both the mask of bits to write and to derive the shift amount from in order to shift the value. In order to ensure that the mask is always a constant, the inst->index shift is performed after the FIELD_PREP_WM16, as this is a runtime value. >From this, we gain compile-time error checking, and in my humble opinion nicer code, as well as a single definition of this macro across the entire codebase to aid in code comprehension. Tested on a RK3399 ROCKPro64, where PCIe still works as expected when accessing an NVMe drive. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-09-11phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variantMichael Riesch
The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing phy-rockchip-inno-csidphy driver, the notable differences being - the control bits in the GRF - the additional reset line Add support for this variant. Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-6-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-10phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset linesMichael Riesch
The RK3588 MIPI CSI-2 DPHY variant requires two reset lines. Add support for different sets of reset lines to the phy-rockchip-inno-csidphy driver as preparation for the introduction of the RK3588 variant. Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-5-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-10phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0Michael Riesch
The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF this offset is perfectly fine (in fact, register 0 is the only one in this register file). Introduce a boolean variable to indicate valid registers and allow writes to register 0. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-4-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-02phy: rockchip-usb: switch to FIELD_PREP_WM16 macroNicolas Frattaroli
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. Remove this driver's HIWORD_UPDATE macro, and replace all instances of it with (hopefully) equivalent FIELD_PREP_WM16 instances. To do this, a few of the defines are being adjusted, as FIELD_PREP_WM16 shifts up the value for us. This gets rid of the icky update(mask, mask) shenanigans. The benefit of using FIELD_PREP_WM16 is that it does more checking of the input, hopefully catching errors. In practice, a shared definition makes code more readable than several different flavours of the same macro, and the shifted value helps as well. I do not have the hardware that uses this particular driver, so it's compile-tested only as far as my own testing goes. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-09-02phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macroNicolas Frattaroli
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. phy-rockchip-samsung-dcphy is actually an exemplary example, where the similarities to FIELD_PREP were spotted and the driver local macro has the same semantics as the new FIELD_PREP_WM16 hw_bitfield.h macro. Still, get rid of FIELD_PREP_HIWORD now that a shared implementation exists, replacing the two instances of it with FIELD_PREP_WM16. This gives us slightly better error checking; the value is now checked to fit in 16 bits. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-09-02phy: rockchip-emmc: switch to FIELD_PREP_WM16 macroNicolas Frattaroli
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. Replace the implementation of the rockchip eMMC PHY driver's HIWORD_UPDATE macro with hw_bitfield.h's FIELD_PREP_WM16. This makes the change more easily reviewable. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-09-01phy: rockchip: usbdp: Remove redundant ternary operatorsLiao Yuanhong
Remove redundant ternary operators to clean up the code. Signed-off-by: Liao Yuanhong <liaoyuanhong@vivo.com> Link: https://lore.kernel.org/r/20250828122401.17441-4-liaoyuanhong@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-20phy: rockchip: naneng-combphy: Convert comma to semicolonChen Ni
Replace comma between expressions with semicolons. Using a ',' in place of a ';' can have unintended side effects. Although that is not the case here, it is seems best to use ';' unless ',' is intended. Found by inspection. No functional change intended. Compile tested only. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Link: https://lore.kernel.org/r/20250814013943.2905307-1-nichen@iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-20phy: remove unneeded 'fast_io' parameter in regmap_configWolfram Sang
When using MMIO with regmap, fast_io is implied. No need to set it again. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250813161517.4746-13-wsa+renesas@sang-engineering.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-13phy: rockchip: naneng-combphy: Add RK3528 supportYao Zi
Rockchip RK3528 integrates one naneng-combphy that is able to operate in PCIe and USB3 mode. The control logic is similar to previous variants of naneng-combphy but the register layout is apparently different from the RK3568 one. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250728102947.38984-7-ziyao@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-13phy: rockchip: naneng-combphy: Add SoC prefix to register definitionsYao Zi
All supported variants of naneng-combphy follow a register layout similar to the RK3568 variant with some exceptions of SoC-specific registers. Add RK3568 prefix for the common set of registers and the corresponding SoC prefix for SoC-specific registers, making usage of definitions clear and preparing for future COMBPHY variants with a different register layout. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250728102947.38984-6-ziyao@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-13phy: rockchip: naneng-combphy: Enable U3 OTG port for RK3568Jonas Karlman
The boot firmware may disable the U3 port early during boot and leave it up to the controller or PHY driver to re-enable U3 when needed. The Rockchip USBDP PHY driver currently does this for RK3576 and RK3588, something the Rockchip Naneng Combo PHY driver never does for RK3568. This may result in USB 3.0 ports being limited to only using USB 2.0 or in special cases not working at all on RK3568. Write to PIPE_GRF USB3OTGx_CON1 reg to ensure the U3 port is enabled when a PHY with PHY_TYPE_USB3 mode is used. Fixes: 7160820d742a ("phy: rockchip: add naneng combo phy for RK3568") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250723072324.2246498-1-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: rockchip-pcie: Properly disable TEST_WRITE strobe signalGeraldo Nascimento
pcie_conf is used to touch TEST_WRITE strobe signal. This signal should be enabled, a little time waited, and then disabled. Current code clearly was copy-pasted and never disables the strobe signal. Adjust the define. While at it, remove PHY_CFG_RD_MASK which has been unused since 64cdc0360811 ("phy: rockchip-pcie: remove unused phy_rd_cfg function"). Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com> Link: https://lore.kernel.org/r/d514d5d5627680caafa8b7548cbdfee4307f5440.1751322015.git.geraldogabriel@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: rockchip-pcie: Enable all four lanes if requiredValmantas Paliksa
Current code enables only Lane 0 because pwr_cnt will be incremented on first call to the function. Let's reorder the enablement code to enable all 4 lanes through GRF. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Valmantas Paliksa <walmis@gmail.com> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/16b610aab34e069fd31d9f57260c10df2a968f80.1751322015.git.geraldogabriel@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-05Merge tag 'phy-for-6.16' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "As usual featuring couple of new driver and bunch of new device support and some driver changes to Freescale, rockchip driver along with couple of yaml binding conversions. New Support: - Qualcomm IPQ5424 qusb2 support, IPQ5018 uniphy-pcie driver - Rockchip usb2 support for RK3562, RK3036 usb2 phy support - Samsung exynos2200 eusb2 phy support and driver refactoring for this support, exynos7870 USBDRD support - Mediatek MT7988 xs-phy support - Broadcom BCM74110 usb phy support - Renesas RZ/V2H(P) usb2 phy support Updates: - Freescale phy rate claculation updates, i.MX95 tuning support - Better error handling for amlogic pcie phy - Rockchip color depth configuration and management support - Yaml binding conversion for RK3399 Type-C and PCIe Phy" * tag 'phy-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits) phy: tegra: p2u: Broaden architecture dependency phy: rockchip: inno-usb2: Add usb2 phy support for rk3562 dt-bindings: phy: rockchip,inno-usb2phy: add rk3562 phy: rockchip: inno-usb2: add phy definition for rk3036 dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible phy: freescale: fsl-samsung-hdmi: Improve LUT search for best clock phy: freescale: fsl-samsung-hdmi: Refactor finding PHY settings phy: freescale: fsl-samsung-hdmi: Rename phy_clk_round_rate phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P) phy: renesas: phy-rcar-gen3-usb2: Sort compatible entries by SoC part number dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family phy: exynos5-usbdrd: support Exynos USBDRD 3.2 4nm controller phy: phy-snps-eusb2: add support for exynos2200 phy: phy-snps-eusb2: refactor reference clock init phy: phy-snps-eusb2: make reset control optional phy: phy-snps-eusb2: make repeater optional phy: phy-snps-eusb2: split phy init code phy: phy-snps-eusb2: refactor constructs names phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory ...
2025-05-14phy: rockchip: inno-usb2: Add usb2 phy support for rk3562Frank Wang
RK3652 has one USB2.0 PHY with two ports, the OTG port support OTG and BC1.2, the SoC provide USB GRF and APB to access the registers. This adds vbus detection function control and make the below tuning to enhance the usb2-phy SQ for RK3562 SoC. - enable pre-emphasis during non-chirp phase - set HS eye height to 425mv Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250415050005.52773-2-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: rockchip: inno-usb2: add phy definition for rk3036Heiko Stuebner
The usb2phy on rk3036 is very similar to rk3128 but not 100% identical. While most registers and bits are the same, a small fraction did get moved around. So we can re-use the phy-tuning function, but need a new set a bits. The biggest change might be that the phy on rk3036 does not support the charger detection, that rk3128 (and newer phys) have. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250503201512.991277-3-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz errorAlgea Cao
When using HDMI PLL frequency division coefficient at 50.25MHz that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to get PHY LANE lock. Although the calculated values are within the allowable range of PHY PLL configuration. In order to fix the PHY LANE lock error and provide the expected 50.25MHz output, manually compute the required PHY PLL frequency division coefficient and add it to ropll_tmds_cfg configuration table. Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250427095124.3354439-1-algea.cao@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: rockchip: samsung-hdptx: Remove unneeded semicolonChen Ni
Remove unnecessary semicolons reported by Coccinelle/coccicheck and the semantic patch at scripts/coccinelle/misc/semicolon.cocci. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Link: https://lore.kernel.org/r/20250415081200.349939-1-nichen@iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-11phy: rockchip: samsung-hdptx: Add high color depth managementCristian Ciocaltea
Add support for 8-bit, 10-bit, 12-bit and 16-bit color depth setup. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Dmitry Baryshkov <dmtiry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-14-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-11phy: rockchip: samsung-hdptx: Optimize internal rate handlingCristian Ciocaltea
Drop the rate parameter from a bunch of internal helpers and, instead, make better use of the newly introduced ->hdmi_cfg.tmds_char_rate driver data. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-13-8cb1678e7663@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.0.4) at 2026-02-21 07:42:41 +0000