summaryrefslogtreecommitdiff
path: root/drivers/pinctrl/meson
AgeCommit message (Collapse)Author
2025-10-01Merge tag 'pinctrl-v6.18-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "We have GPIO awareness in the pin control core and an interesting AAEON driver. Core changes: - Allow pins to be identified/marked as GPIO mode with a special callback. The pin controller core is now "aware" if a pin is in GPIO mode if the callback is implemented in the driver, and can thus be marked as "strict", i.e. disallowing simultaneous use of a line as GPIO and another function such as I2C. This is enabled in the Qualcomm TLMM driver and also implemeted from day 1 in the new Broadcom STB driver - Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL to better describe what the config is doing, as well as making it more intuitive what shall be returned when reading this property New drivers: - Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver - Qualcomm Glymur family pin controller driver - Broadcom STB family pin controller driver - Tegra186 pin controller driver - AAEON UP pin controller support. This is some special pin controller that works as an external advanced line MUX and amplifier for signals from an Intel SoC. A cooperative effort with the GPIO maintainer was needed to reach a solution where we reuse code from the GPIO aggregator/forwarder driver - Renesas RZ/T2H and RZ/N2H pin controller support - Axis ARTPEC-8 subdriver for the Samsung pin controller driver Improvements: - Output enable (OEN) support in the Renesas RZG2L driver - Properly support bias pull up/down in the pinctrl-single driver - Move over all GPIO portions using generic MMIO GPIO to the new generic GPIO chip management which has a nice and separate API - Proper DT bindings for some older Broadcom SoCs - External GPIO (EGPIO) support in the Qualcomm SM8250 Deleted code: - Dropped the now unused Samsung S3C24xx drivers" * tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits) pinctrl: use more common syntax for compound literals pinctrl: Simplify printks with pOF format pinctrl: qcom: Add SDM660 LPASS LPI TLMM dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets pinctrl: qcom: Add glymur pinctrl driver dt-bindings: pinctrl: qcom: Add Glymur pinctrl pinctrl: qcom: sm8250: Add egpio support pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL pinctrl: keembay: fix double free in keembay_build_functions() pinctrl: spacemit: fix typo in PRI_TDI pin name pinctrl: eswin: Fix regulator error check and Kconfig dependency pinctrl: bcm: Add STB family pin controller driver dt-bindings: pinctrl: Add support for Broadcom STB pin controller pinctrl: qcom: make the pinmuxing strict pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions pinctrl: qcom: add infrastructure for marking pin functions as GPIOs pinctrl: allow to mark pin functions as requestable GPIOs pinctrl: qcom: use generic pin function helpers pinctrl: make struct pinfunction a pointer in struct function_desc ...
2025-09-08pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVELLinus Walleij
This generic pin config property is confusingly named so let's rename it to make things clearer. There are already drivers in the tree that use PIN_CONFIG_OUTPUT to *read* the value of an output driven pin, which is a big semantic confusion for the head: are we then reading the setting of the output or the actual value/level that is put out on the pin? We already have PIN_CONFIG_OUTPUT_ENABLE that turns on driver buffers for output, so this can by logical conclusion only drive the voltage level if it should be any different. But if we read the pin, are we then reading the *setting* of the output value or the *actual* value we can see on the line? If the pin has not first been set into output mode with PIN_CONFIG_OUTPUT_ENABLE, but is instead in some input mode or tristate, what will reading this property actually return? Reading the current users reading this property it is clear that what we read is the logical level of the pin as 0 or 1 depending on if it is low or high. Rename it to PIN_CONFIG_LEVEL so it is crystal clear that we set or read the voltage level of the pin and nothing else. Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-28pinctrl: meson-gxl: add missing i2c_d pinmuxDa Xue
Amlogic GXL has 4 I2C attached to gpio-periphs. I2C_D is on GPIOX_10/11. Add the relevant func 3 pinmux per the datasheet for S805X/S905X/S905D. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Signed-off-by: Da Xue <da@libre.computer> Link: https://lore.kernel.org/20250821233335.1707559-1-da@libre.computer Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-19pinctrl: meson-g12a: add GPIOC_7 pcie_clkreqn pinmuxDa Xue
Amlogic G12 exposes PCIe clock request signal on GPIOC_7 pinmux func 1 Add the relevant pinmux and pin groups Signed-off-by: Da Xue <da@libre.computer> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/20250814181236.1956731-1-da@libre.computer Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-18pinctrl: meson: Fix typo in device table macroAlexey Gladkov
The typo when using the MODULE_DEVICE_TABLE macro was not noticeable because the macro was defined only if the module was built as a separate module. Cc: Xianwei Zhao <xianwei.zhao@amlogic.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-amlogic@lists.infradead.org Cc: linux-gpio@vger.kernel.org Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202507220009.8HKbNP16-lkp@intel.com/ Signed-off-by: Alexey Gladkov <legion@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/e548b7761302defec15aa2098172eabb1ce1ad4a.1755170493.git.legion@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-08-07treewide: rename GPIO set callbacks back to their original namesBartosz Golaszewski
The conversion of all GPIO drivers to using the .set_rv() and .set_multiple_rv() callbacks from struct gpio_chip (which - unlike their predecessors - return an integer and allow the controller drivers to indicate failures to users) is now complete and the legacy ones have been removed. Rename the new callbacks back to their original names in one sweeping change. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-06-24pinctrl: amlogic: Staticize some local structsLinus Walleij
Sparse complains: sparse warnings: (new ones prefixed by >>) >> drivers/pinctrl/meson/pinctrl-amlogic-a4.c:126:24: sparse: sparse: symbol 'multi_mux_s7' was not declared. Should it be static? >> drivers/pinctrl/meson/pinctrl-amlogic-a4.c:135:28: sparse: sparse: symbol 's7_priv_data' was not declared. Should it be static? >> drivers/pinctrl/meson/pinctrl-amlogic-a4.c:140:24: sparse: sparse: symbol 'multi_mux_s6' was not declared. Should it be static? >> drivers/pinctrl/meson/pinctrl-amlogic-a4.c:154:28: sparse: sparse: symbol 's6_priv_data' was not declared. Should it be static? Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202506122145.wWAtKBoy-lkp@intel.com/ Cc: Xianwei Zhao <xianwei.zhao@amlogic.com> Fixes: 1f8e5dfddaa7 ("pinctrl: meson: support amlogic S6/S7/S7D SoC") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20250624-amlogic-a4-fix-v1-1-03f0856d10cb@linaro.org
2025-06-24pinctrl: meson-g12a: add g12b pwm groupsDa Xue
G12B and SM1 have additional PWM pinmuxes for b, c, and d. Signed-off-by: Da Xue <da@libre.computer> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250619022337.43900-1-da@libre.computer Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-06-10pinctrl: meson: support amlogic S6/S7/S7D SoCXianwei Zhao
In some Amlogic SoCs, to save register space or due to some abnormal arrangements, two sets of pins share one mux register. A group starting from pin0 is the main pin group, which acquires the register address through DTS and has management permissions, but the register bit offset is undetermined. Another GPIO group as a subordinate group. Some pins mux use share register and bit offset from bit0 . But this group do not have register management permissions. This submission implements this situation. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250527-s6-s7-pinctrl-v3-3-44f6a0451519@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-06-10pinctrl: meson: a4: remove special data processingXianwei Zhao
According to the data specifications of Amlogic's existing SoCs, the function register offset and the bit offset are the same value among various chips. Therefore, general processing can be carried out without the need for private data modification. Drop special data processing. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250527-s6-s7-pinctrl-v3-2-44f6a0451519@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-05-30Merge tag 'pinctrl-v6.16-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "An especially linear and sparse improvement and new drivers release. Nothing exciting. The biggest change in Bartosz changes to make gpiochip set/get calls return error codes (something we should have fixed ages ago but is now finally getting fixed.) Core changes: - Add the devres devm_pinctrl_register_mappings() call that can register some pin control machine mappings and have them go away with the associated device New drivers: - Support for the Mediatek MT6893 and MT8196 SoCs - Support for the Renesas RZ/V2N SoC - Support for the NXP Freescale i.MX943 SoC Improvements: - Per-SoC suspend/resume callbacks in the Samsung drivers - Set all pins as input (High-Z) at probe in the MCP23S08 driver - Switch most GPIO chips to use the setters/getters with a return value - EGPIO support in the Qualcomm QCM2290 driver - Fix up the number of available GPIO lines in Qualcomm QCS8300 and QCS615" * tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits) pinctrl: freescale: Add support for imx943 pinctrl pinctrl: core: add devm_pinctrl_register_mappings() pinctrl: remove extern specifier for functions in machine.h pinctrl: mediatek: eint: Fix invalid pointer dereference for v1 platforms pinctrl: freescale: Enable driver if platform is enabled. pinctrl: freescale: Depend imx-scu driver on OF pinctrl: armada-37xx: propagate error from armada_37xx_pmx_set_by_name() pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get_direction() pinctrl: armada-37xx: propagate error from armada_37xx_pmx_gpio_set_direction() pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get() pinctrl: armada-37xx: propagate error from armada_37xx_gpio_direction_output() pinctrl: armada-37xx: set GPIO output value before setting direction pinctrl: armada-37xx: use correct OUTPUT_VAL register for GPIOs > 31 pinctrl: meson: Drop unused aml_pctl_find_group_by_name() pinctrl: at91: Fix possible out-of-boundary access pinctrl: add stubs for OF-specific pinconf functions pinctrl: qcom: correct the ngpios entry for QCS8300 pinctrl: qcom: correct the ngpios entry for QCS615 dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300 dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615 ...
2025-05-13pinctrl: meson: Drop unused aml_pctl_find_group_by_name()Krzysztof Kozlowski
aml_pctl_find_group_by_name() is not used anywhere, as reported by W=1 clang build: pinctrl-amlogic-a4.c:600:2: error: unused function 'aml_pctl_find_group_by_name' [-Werror,-Wunused-function] Fixes: 6e9be3abb78c ("pinctrl: Add driver support for Amlogic SoCs") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/20250509150114.299962-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: amlogic-a4: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-6-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: meson: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250408-gpiochip-set-rv-pinctrl-part1-v1-5-c9d521d7c8c7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: meson: Do not enable by default during compile testingKrzysztof Kozlowski
Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250404115719.309999-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-04-15pinctrl: meson: define the pull up/down resistor value as 60 kOhmMartin Blumenstingl
The public datasheets of the following Amlogic SoCs describe a typical resistor value for the built-in pull up/down resistor: - Meson8/8b/8m2: not documented - GXBB (S905): 60 kOhm - GXL (S905X): 60 kOhm - GXM (S912): 60 kOhm - G12B (S922X): 60 kOhm - SM1 (S905D3): 60 kOhm The public G12B and SM1 datasheets additionally state min and max values: - min value: 50 kOhm for both, pull-up and pull-down - max value for the pull-up: 70 kOhm - max value for the pull-down: 130 kOhm Use 60 kOhm in the pinctrl-meson driver as well so it's shown in the debugfs output. It may not be accurate for Meson8/8b/8m2 but in reality 60 kOhm is closer to the actual value than 1 Ohm. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/20250329190132.855196-1-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-22pinctrl: amlogic-a4: Drop surplus semicolonLinus Walleij
The kernel bots complain about untidy code found using coccinelle, fix it up. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202503212354.Hx2qaDRe-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-04pinctrl: meson: fix pin input property for a4Xianwei Zhao
The register of pin input attribute means the opposite. value of reigster meaning is 1 for input and 0 for output. So fix it. Fixes: 6e9be3abb78c ("pinctrl: Add driver support for Amlogic SoCs") Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250303-fix-a4-pinctl-v1-1-6579888b4272@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28pinctrl: Add driver support for Amlogic SoCsXianwei Zhao
Add a new pinctrl driver for Amlogic SoCs. All future Amlogic SoCs pinctrl drives use this, such A4, A5, S6, S7 etc. To support new Amlogic SoCs, only need to add the corresponding dts file. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250212-amlogic-pinctrl-v5-3-282bc2516804@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-23pinctrl: meson: Constify some structuresChristophe JAILLET
The following structures are not modified in these drivers. - struct meson_bank - struct meson_pmx_bank - struct meson_pmx_func - struct meson_pmx_group - struct meson_pinctrl_data - struct meson_axg_pmx_data Constifying these structures moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 10818 11696 0 22514 57f2 drivers/pinctrl/meson/pinctrl-amlogic-c3.o 17198 17680 0 34878 883e drivers/pinctrl/meson/pinctrl-amlogic-t7.o 14161 11200 0 25361 6311 drivers/pinctrl/meson/pinctrl-meson8b.o 17348 12512 0 29860 74a4 drivers/pinctrl/meson/pinctrl-meson8.o 3070 324 0 3394 d42 drivers/pinctrl/meson/pinctrl-meson8-pmx.o 9317 9648 0 18965 4a15 drivers/pinctrl/meson/pinctrl-meson-a1.o 12115 11664 0 23779 5ce3 drivers/pinctrl/meson/pinctrl-meson-axg.o 2470 120 0 2590 a1e drivers/pinctrl/meson/pinctrl-meson-axg-pmx.o 15125 15224 0 30349 768d drivers/pinctrl/meson/pinctrl-meson-g12a.o 13800 10160 0 23960 5d98 drivers/pinctrl/meson/pinctrl-meson-gxbb.o 13040 9648 0 22688 58a0 drivers/pinctrl/meson/pinctrl-meson-gxl.o 20507 1132 48 21687 54b7 drivers/pinctrl/meson/pinctrl-meson.o 12212 12880 0 25092 6204 drivers/pinctrl/meson/pinctrl-meson-s4.o After: ===== text data bss dec hex filename 22242 248 0 22490 57da drivers/pinctrl/meson/pinctrl-amlogic-c3.o 34638 248 0 34886 8846 drivers/pinctrl/meson/pinctrl-amlogic-t7.o 25137 232 0 25369 6319 drivers/pinctrl/meson/pinctrl-meson8b.o 29604 232 0 29836 748c drivers/pinctrl/meson/pinctrl-meson8.o 3070 324 0 3394 d42 drivers/pinctrl/meson/pinctrl-meson8-pmx.o 18725 248 0 18973 4a1d drivers/pinctrl/meson/pinctrl-meson-a1.o 23539 248 0 23787 5ceb drivers/pinctrl/meson/pinctrl-meson-axg.o 2470 120 0 2590 a1e drivers/pinctrl/meson/pinctrl-meson-axg-pmx.o 30101 256 0 30357 7695 drivers/pinctrl/meson/pinctrl-meson-g12a.o 23688 248 0 23936 5d80 drivers/pinctrl/meson/pinctrl-meson-gxbb.o 22416 248 0 22664 5888 drivers/pinctrl/meson/pinctrl-meson-gxl.o 20507 1132 48 21687 54b7 drivers/pinctrl/meson/pinctrl-meson.o 24820 248 0 25068 61ec drivers/pinctrl/meson/pinctrl-meson-s4.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/f74e326bd7d48003c06219545bad7c2ef1a84bf8.1723053850.git.christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: add missing MODULE_DESCRIPTION() macrosJeff Johnson
When ARCH=x86, make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/bcm/pinctrl-bcm4908.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08_i2c.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08_spi.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/meson/pinctrl-meson.o Add the missing invocation of the MODULE_DESCRIPTION() macro to all files which have a MODULE_LICENSE(). This includes many meson drivers which, although they did not produce a warning with the x86 allmodconfig configuration, may cause this warning with ARM or ARM64 configurations. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> # for Amlogic Pinctrl drivers Link: https://lore.kernel.org/r/20240610-md-drivers-pinctrl-v1-1-68462e3d960c@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-03-28pinctrl/meson: fix typo in PDM's pin nameJan Dakinevich
Other pins have _a or _x suffix, but this one doesn't have any. Most likely this is a typo. Fixes: dabad1ff8561 ("pinctrl: meson: add pinctrl driver support for Meson-A1 SoC") Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Message-ID: <20240325113058.248022-1-jan.dakinevich@salutedevices.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-25pinctrl: Add driver support for Amlogic T7 SoCsHuqiang Qin
Add a new pinctrl driver for Amlogic T7 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20230922094342.637251-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-23pinctrl: use capital "OR" for multiple licenses in SPDXKrzysztof Kozlowski
Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Correct also the placement of SPDX identifier in pinctrl-meson-axg files: WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823085546.116494-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: Replace the IRQ number in the driver with the IRQID macro definitionHuqiang Qin
Replacing IRQ numbers with IRQID macro definitions makes driver code easier to understand. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230724060108.1403662-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-23pinctrl: Add driver support for Amlogic C3 SoCsHuqiang Qin
Add a new pinctrl driver for Amlogic C3 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: Explicitly include correct DT includesRob Herring
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-16pinctrl: meson-axg: add missing GPIOA_18 gpio groupMartin Hundebøll
Without this, the gpio cannot be explicitly mux'ed to its gpio function. Fixes: 83c566806a68a ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Cc: stable@vger.kernel.org Signed-off-by: Martin Hundebøll <martin@geanix.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Link: https://lore.kernel.org/r/20230512064925.133516-1-martin@geanix.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-09-08pinctrl: meson: Switch to use fwnode instead of of_nodeAndy Shevchenko
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220905180034.73132-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-04Merge tag 'intel-gpio-v5.19-1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel intel-gpio for v5.19-1 * Introduce helpers to iterate over GPIO chip nodes and covert some drivers The following is an automated git shortlog grouped by driver: gpiolib: - Introduce a helper to get first GPIO controller node - Introduce gpiochip_node_count() helper - Introduce for_each_gpiochip_node() loop helper pinctrl: - meson: Replace custom code by gpiochip_node_count() call - meson: Enable COMPILE_TEST - meson: Rename REG_* to MESON_REG_* - armada-37xx: Reuse GPIO fwnode in armada_37xx_irqchip_register() - armada-37xx: Switch to use fwnode instead of of_node - samsung: Switch to use for_each_gpiochip_node() helper - samsung: Drop redundant node parameter in samsung_banks_of_node_get() - npcm7xx: Switch to use for_each_gpiochip_node() helper - renesas: rza1: Switch to use for_each_gpiochip_node() helper - renesas: rza1: Replace custom code by gpiochip_node_count() call - stm32: Switch to use for_each_gpiochip_node() helper - stm32: Replace custom code by gpiochip_node_count() call
2022-04-22pinctrl: meson: fix unused variable warningQianggui Song
The kernel test robot reported a warning as below: >> drivers/pinctrl/meson/pinctrl-meson-s4.c:178:27: warning: unused variable 'tdm_sclk1_c_pins' [-Wunused-const-variable] static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; Fix it by adding missing description about this pins Fixes: 775214d389c2 ("pinctrl: meson: add pinctrl driver support for Meson-S4 Soc") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220330023720.18238-1-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-04-18pinctrl: meson: Replace custom code by gpiochip_node_count() callAndy Shevchenko
Since we have generic function to count GPIO controller nodes under a given device, there is no need to open code it. Replace custom code by gpiochip_node_count() call. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2022-04-18pinctrl: meson: Enable COMPILE_TESTAndy Shevchenko
Enable COMPILE_TEST for a better test coverage. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2022-04-18pinctrl: meson: Rename REG_* to MESON_REG_*Andy Shevchenko
Currently compilation test fails on x86 due to name collision. The usual way to fix that is to move both conflicting parts to their own namespaces. Rename REG_* to MESON_REG_* as a prerequisite for enabling COMPILE_TEST. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2022-01-30pinctrl: meson: add pinctrl driver support for Meson-S4 SocQianggui Song
Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the same register layout as the previous Meson-A1. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-01-24pinctrl: meson-g12a: add more pwm_f optionsGary Bisson
Add missing PWM_F pin muxing for GPIOA_11 and GPIOZ_12. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220112211642.2248901-2-gary.bisson@boundarydevices.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-11-05pinctrl/meson: enable building as modulesKevin Hilman
Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules. The default is still built-in, this only adds the option of building as modules. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-16pinctrl: meson: pinctrl-meson-a1: Remove unused const variable ↵Lee Jones
'i2c_slave_groups' It has never been used. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/meson/pinctrl-meson-a1.c:749:27: warning: ‘i2c_slave_groups’ defined but not used [-Wunused-const-variable=] 749 | static const char const i2c_slave_groups[] = { | ^~~~~~~~~~~~~~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Qianggui Song <qianggui.song@amlogic.com> Cc: linux-amlogic@lists.infradead.org Link: https://lore.kernel.org/r/20200713144930.1034632-24-lee.jones@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07pinctrl: meson: fix drive strength register and bit calculationHyeonki Hong
If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two or more registers. However, when register and bit were calculated, the first register defined in the bank was used, and the bit was calculated based on the first pin. This causes problems in setting the driving strength. The following method was used to solve this problem: A bit is calculated first using predefined strides. Then, If the bit is 32 or more, the register is changed by the quotient of the bit divided by 32. And the bit is set to the remainder. Signed-off-by: Hyeonki Hong <hhk7734@gmail.com> Link: https://lore.kernel.org/r/20200618025916.GA19368@home-desktop Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-04-28pinctrl: meson: wire up the gpio_chip's set_config callbackMartin Blumenstingl
Use gpiochip_generic_config for the gpio_chip's set_config callback so GPIO flags like GPIO_PULL_UP or GPIO_PULL_DOWN can be used in the board .dts descriptions. This is required for some Meson8m2 boards where GPIO_BSD_EN provides the "MUTE" signal and requires enabling the internal pull-up resistor. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200417183349.1283092-3-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-04-28pinctrl: meson: implement the gpio_chip get_direction callbackMartin Blumenstingl
Implement the get_direction callback so we read the direction from the actual GPIO controller register. This is recommended by the gpio_chip kernel doc. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200417183349.1283092-2-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-04-02Merge tag 'pinctrl-v5.7-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.7 kernel cycle. There are no core changes this time, only driver developments: - New driver for the Dialog Semiconductor DA9062 Power Management Integrated Circuit (PMIC). - Renesas SH-PFC has improved consistency, with group and register checks in the configuration checker. - New subdriver for the Qualcomm IPQ6018. - Add the RGMII pin control functionality to Qualcomm IPQ8064. - Performance and code quality cleanups in the Mediatek driver. - Improve the Broadcom BCM2835 support to cover all the GPIOs that exist in it. - The Allwinner/Sunxi driver properly masks non-wakeup IRQs on suspend. - Add some missing groups and functions to the Ingenic driver. - Convert some of the Freescale device tree bindings to use the new and all improved JSON YAML markup. - Refactorings and support for the SFIO/GPIO in the Tegra194 SoC driver. - Support high impedance mode in the Spreadtrum/Unisoc driver" * tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits) pinctrl: qcom: fix compilation error pinctrl: qcom: use scm_call to route GPIO irq to Apps pinctrl: sprd: Add pin high impedance mode support pinctrl: sprd: Use the correct pin output configuration pinctrl: tegra: Add SFIO/GPIO programming on Tegra194 pinctrl: tegra: Renumber the GG.0 and GG.1 pins pinctrl: tegra: Do not add default pin range on Tegra194 pinctrl: tegra: Pass struct tegra_pmx for pin range check pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo pinctrl: tegra: Fix whitespace issues for improved readability pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow pinctrl: freescale: drop the dependency on ARM64 for i.MX8M Revert "pinctrl: mvebu: armada-37xx: use use platform api" dt-bindings: pinctrl: at91: Fix a typo ("descibe") pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm pinctrl: sprd: Fix the kconfig warning pinctrl: ingenic: add hdmi-ddc pin control group pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member pinctrl: sprd: Allow the SPRD pinctrl driver building into a module pinctrl: Export some needed symbols at module load time ...
2020-03-12pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxmIgor Vavro
Add the tsin pinctrl definitions needed for integrated DVB hardware support on Meson GXBB/GXL/GXM boards. changes in v2 - fix ordering and numbering of uart_c ping flagged by Otto in [1] [1] http://lists.infradead.org/pipermail/linux-amlogic/2020-March/015906.html Signed-off-by: Igor Vavro <afl2001@gmail.com> [updated commit message] Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/1583377666-13378-1-git-send-email-christianshewitt@gmail.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-21pinctrl: meson-gxl: fix GPIOX sdio pinsNicolas Belin
In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused any issue so far because devices using these pins always take both pins so the resulting configuration is OK. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Nicolas Belin <nbelin@baylibre.com> Link: https://lore.kernel.org/r/1582204512-7582-1-git-send-email-nbelin@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-29Merge tag 'pinctrl-v5.6-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes, nothing too exciting about this. Some changes hit arch/sh and arch/arm but are well isolated and acknowledged by the respective arch maintainers. Core changes: - Dropped the chained IRQ setup callback into GPIOLIB as we got rid of the last users of that in this changeset. New drivers: - New driver for Ingenic X1830. - New driver for Freescale i.MX8MP. Driver enhancements: - Fix all remaining Intel drivers to pass their IRQ chips along with the GPIO chips. - Intel Baytrail allocates its irqchip dynamically. - Intel Lynxpoint is thoroughly rewritten and modernized. - Aspeed AST2600 pin muxing and configuration is much improved. - Qualcomm SC7180 functions are updated and wakeup interrupt map is provided. - A whole slew of Renesas SH-PFC cleanups and improvements. - Fix up the Intel DT bindings to use the generic YAML DT bindings schema (a first user of this)" * tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: madera: Remove extra blank line pinctrl: qcom: Don't lock around irq_set_irq_wake() pinctrl: mvebu: armada-37xx: use use platform api gpio: Drop the chained IRQ handler assign function pinctrl: freescale: Add i.MX8MP pinctrl driver support dt-bindings: imx: Add pinctrl binding doc for i.MX8MP pinctrl: tigerlake: Tiger Lake uses _HID enumeration pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID pinctrl: iproc: Use platform_get_irq_optional() to avoid error message pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema pinctrl: intel: Pass irqchip when adding gpiochip pinctrl: intel: Add GPIO <-> pin mapping ranges via callback pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins pinctrl: sunrisepoint: Add missing Interrupt Status register offset pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers pinctrl: artpec6: fix __iomem on reg in set pinctrl: ingenic: Use devm_platform_ioremap_resource() pinctrl: ingenic: Factorize irq_set_type function pinctrl: ingenic: Remove duplicated ingenic_chip_info structures ...
2020-01-07pinctrl: meson: meson8b: add the GPIOH pinmux settings for ETH_RXD{2,3}Martin Blumenstingl
GPIOH_5 and GPIOH_6 can have two Ethernet related functions: - GPIOH_5 can be ETH_TXD1 or ETH_RXD3 - GPIOH_6 can be ETH_TXD0 or ETH_RXD2 Add the bits for eth_rxd3_h and eth_rxd2_h so the ETH_RXD function can be disabled when using the ETH_TXD function of GPIOH_{5,6}. No problem was observed so far, but in theory this could lead to two different signals being routed to the same pad (which could break Ethernet). These settings were found in the public "Amlogic Ethernet controller user guide": http://openlinux.amlogic.com/@api/deki/files/75/=Amlogic_Ethenet_controller_user_Guide.pdf Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20191226191425.3797490-1-martin.blumenstingl@googlemail.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07pinctrl: meson: Fix wrong shift value when get drive-strengthQianggui Song
In meson_pinconf_get_drive_strength, variable bit is calculated by meson_calc_reg_and_bit, this value is the offset from the first pin of a certain bank to current pin, while Meson SoCs use two bits for each pin to depict drive-strength. So a left shift by 1 should be done or node pinconf-pins shows wrong message. Fixes: 6ea3e3bbef37 ("pinctrl: meson: add support of drive-strength-microamp") Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/20191226023734.9631-1-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-12pinctrl: meson-axg: Use the correct style for SPDX License IdentifierNishad Kamdar
This patch corrects the SPDX License Identifier style in header file related Meson axg SoC pinctrl driver. It assigns explicit block comment for the SPDX License Identifier. Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Link: https://lore.kernel.org/r/bcb86aa22d8d8499502bbd8c54a364be24886a86.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-19pinctrl: meson: add pinctrl driver support for Meson-A1 SoCQianggui Song
Meson A1 SoC share the same register layout of pinmux with previous Meson-G12A, however there is difference for gpio and pin config register in A1. The main difference is that registers before A1 are grouped by function while those of A1 are by bank. The new register layout is as below: /* first bank */ /* addr */ - P_PADCTRL_GPIOP_I base + 0x00 << 2 - P_PADCTRL_GPIOP_O base + 0x01 << 2 - P_PADCTRL_GPIOP_OEN base + 0x02 << 2 - P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2 - P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2 - P_PADCTRL_GPIOP_DS base + 0x05 << 2 /* second bank */ - P_PADCTRL_GPIOB_I base + 0x10 << 2 - P_PADCTRL_GPIOB_O base + 0x11 << 2 - P_PADCTRL_GPIOB_OEN base + 0x12 << 2 - P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2 - P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2 - P_PADCTRL_GPIOB_DS base + 0x15 << 2 Each bank contains at least 6 registers to be configured, if one bank has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24 ,0x25 according to above register layout. For previous chips, registers are grouped according to their functions while registers of A1 are according to bank.Also note that there is no AO bank any more in A1. Current Meson pinctrl driver can cover such change by using base address of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen make wrong value to reg_ds for Socs that do not support drive-strength like AXG.To make things simple, add an extra dt parser function for a1 and remain the old dt parser function for only reg parsing. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-19pinctrl: meson: add a new callback for SoCs fixupQianggui Song
In meson_pinctrl_parse_dt, it contains two parts: reg parsing and SoC relative fixup for AO. Several fixups in the same code make it hard to maintain, so move all fixups to each SoC's callback and make meson_pinctrl_parse_dt just do the reg parsing, separate these two parts.Overview of all current Meson SoCs fixup is as below: +------+--------------------------------------+--------------------------+ | | | | | SoC | EE domain | AO domain | +------+--------------------------------------+--------------------------+ |m8 | parse regs: | parse regs: | |m8b | gpio,mux,pull,pull-enable(skip ds) | gpio,mux,pull(skip ds)| |gxl | fixup: | fixup: | |gxbb | no | pull-enable = pull; | |axg | | | +------+--------------------------------------+--------------------------+ |g12a | parse regs: | parse regs: | |sm1 | gpio,mux,pull,pull-enable,ds | gpio,mux,ds | | | fixup: | fixup: | | | no | pull = gpio; | | | | pull-enable = gpio; | +------+--------------------------------------+--------------------------+ |a1 or | parse regs: | |later | gpio/mux (without ao domain) | |SoCs | fixup: | | | pull = gpio; pull-enable = gpio; ds = gpio; | +------+-----------------------------------------------------------------+ Since m8-axg share the same ao fixup, make a common function meson8_aobus_parse_dt_extra to do the job. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-23 06:10:46 +0000