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path: root/drivers
AgeCommit message (Expand)Author
2013-01-31drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_APaulo Zanoni
2013-01-31drm/i915: don't run hsw power well code on !hswDaniel Vetter
2013-01-31drm/i915: kill cargo-culted locking from power well codeDaniel Vetter
2013-01-31drm/i915: Only run idle processing from i915_gem_retire_requests_workerChris Wilson
2013-01-31drm/i915: Fix CAGF for HSWBen Widawsky
2013-01-31drm/i915: Reclaim GTT space for failed PPGTTBen Widawsky
2013-01-31drm/i915: remove intel_gtt structureBen Widawsky
2013-01-31drm/i915: Add probe and remove to the gtt opsBen Widawsky
2013-01-31drm/i915: extract hw ppgtt setup/cleanup codeDaniel Vetter
2013-01-31drm/i915: pte_encode is gen6+Daniel Vetter
2013-01-31drm/i915: vfuncs for ppgttDaniel Vetter
2013-01-31drm/i915: vfuncs for gtt_clear_range/insert_entriesDaniel Vetter
2013-01-31drm/i915: Error state should print /sys/kernel/debugBen Widawsky
2013-01-31drm/i915: move DP save/restore into i915_ums.cDaniel Vetter
2013-01-31drm/i915: dont save/restore VGA state for kmsDaniel Vetter
2013-01-31drm/i915: extract ums suspend/resume into i915_ums.cDaniel Vetter
2013-01-28drm/i915: move modeset checks out of save/restore_modeset_regDaniel Vetter
2013-01-28drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky
2013-01-28drm/i915: turn on the power well before suspendingPaulo Zanoni
2013-01-28drm/i915: set TRANSCODER_EDP even earlierPaulo Zanoni
2013-01-26drm/i915: only disable enabled planes on intel_fb_restore_modePaulo Zanoni
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni
2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä
2013-01-26drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLVVille Syrjälä
2013-01-26drm/i915: VLV doesn't have SDVOVille Syrjälä
2013-01-26drm/i915: Always use adpa_regVille Syrjälä
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Set display_mmio_offset for VLVVille Syrjälä
2013-01-24drm/i915: GPIO/GMBUS registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä
2013-01-24drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä
2013-01-24drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä
2013-01-24drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä
2013-01-24drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä
2013-01-24drm/i915: DSPFW registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: VLV_DDL is VLV only and needs an offsetVille Syrjälä
2013-01-24drm/i915: Cursor registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Pipe registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Primary plane registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: PIPE M/N registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: VLV_VIDEO_DIP_CTL is for VLV onlyVille Syrjälä
2013-01-24drm/i915: Per-pipe PP registers are for VLV onlyVille Syrjälä
2013-01-24drm/i915: AUD_VID_DID needs an offset on VLVVille Syrjälä
2013-01-24drm/i915: Add display_display_mmio_offset to intel_device_infoVille Syrjälä
2013-01-24drm/i915: Convert intel_dp to enum portVille Syrjälä
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