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path: root/drivers
AgeCommit message (Expand)Author
2021-03-08drm/i915: Call primary encoder's .get_config() from MST .get_config()Ville Syrjälä
2021-03-05drm/i915: Fix DSI TE max_vblank_count handlingVille Syrjälä
2021-03-05drm/i915: Return zero as the scanline counter for disabled pipesVille Syrjälä
2021-03-05drm/i915: Don't try to query the frame counter for disabled pipesVille Syrjälä
2021-03-05drm/i915: Move pipe enable/disable tracepoints to intel_crtc_vblank_{on,off}()Ville Syrjälä
2021-03-04drm/i915/edp: enable eDP MSO during link trainingJani Nikula
2021-03-04drm/i915/edp: modify fixed and downclock modes for MSOJani Nikula
2021-03-04drm/i915/mso: add splitter state checkJani Nikula
2021-03-04drm/i915/mso: add splitter state readout for platforms that support itJani Nikula
2021-03-03drm/i915: Clean up verify_wm_state()Ville Syrjälä
2021-03-03drm/i915: Check tgl+ SAGV watermarks properlyVille Syrjälä
2021-03-03drm/i915: Introduce SAGV transtion watermarkVille Syrjälä
2021-03-03drm/i915: Stuff SAGV watermark into a sub-structureVille Syrjälä
2021-03-03drm/i915: Print wm changes if sagv_wm0 changesVille Syrjälä
2021-03-03drm/i915: Zero out SAGV wm when we don't have enough DDB for itVille Syrjälä
2021-03-03drm/i915: Fix TGL+ plane SAGV watermark programmingVille Syrjälä
2021-03-03drm/i915: Readout conn_state->max_bpcVille Syrjälä
2021-03-02drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()Lyude Paul
2021-03-02drm/i915/gen9bc: Handle TGP PCH during suspend/resumeTejas Upadhyay
2021-02-24drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain namesImre Deak
2021-02-23drm/i915/display: Do not allow DC3CO if PSR SF is enabledGwan-gyeong Mun
2021-02-22drm/i915/reg: add stream splitter configuration definitionsJani Nikula
2021-02-22drm/i915/edp: read sink MSO configuration for eDP 1.4+Jani Nikula
2021-02-22drm/i915/edp: always add fixed mode to probed modes in ->get_modes()Jani Nikula
2021-02-22drm/i915/edp: reject modes with dimensions other than fixed modeJani Nikula
2021-02-22drm/i915/display: Set source_support even if panel do not support PSRJosé Roberto de Souza
2021-02-22drm/i915/display: Remove some redundancy around CAN_PSR()José Roberto de Souza
2021-02-22drm/i915/display: Only write to register in intel_psr2_program_trans_man_trk_...José Roberto de Souza
2021-02-22drm/i915/display: Rename for_each_intel_encoder.*_can_psr to for_each_intel_e...José Roberto de Souza
2021-02-22drm/i915/display: Allow PSR2 selective fetch to be enabled at run-timeJosé Roberto de Souza
2021-02-20drm/i915/vbt: update DP max link rate tableLee Shawn C
2021-02-18drm/i915: Wait for scanout to stop when sanitizing planesVille Syrjälä
2021-02-18drm/i915: Nuke INTEL_OUTPUT_FORMAT_INVALIDVille Syrjälä
2021-02-17drm/i915: Remove dead code from skl_pipe_wm_get_hw_state()José Roberto de Souza
2021-02-17drm/i915: Enable -WuninitializedNathan Chancellor
2021-02-16drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routingVille Syrjälä
2021-02-16drm/i915: Relocate icl_sanitize_encoder_pll_mapping()Ville Syrjälä
2021-02-16drm/i915: Use .disable_clock() for pll sanitationVille Syrjälä
2021-02-16drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Extract _cnl_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()Ville Syrjälä
2021-02-16drm/i915: Sprinkle a few missing locks around shared DDI clock registersVille Syrjälä
2021-02-16drm/i915: Use intel_de_rmw() for DDI clock routingVille Syrjälä
2021-02-16drm/i915: Extract icl+ .{enable,disable}_clock() vfuncsVille Syrjälä
2021-02-16drm/i915: Convert DG1 over to .{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i195: Extract cnl_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Extract skl_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Extract hsw_ddi_{enable,disable}_clock()Ville Syrjälä
2021-02-16drm/i915: Introduce .{enable,disable}_clock() encoder vfuncsVille Syrjälä
2021-02-16drm/i915: Use intel_ddi_clk_select() for FDIVille Syrjälä
generated by cgit v1.2.3 (git 2.0.4) at 2026-07-20 23:34:23 +0000