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8 daysMerge tag 'rproc-v7.4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux Pull remoteproc updates from Bjorn Andersson: - Add Qualcomm QMI Thermal Mitigation Device support for PAS-managed remote processors, with cooling device bindings and configurations for Hamoa, Kodiak, Lemans, Talos, Monaco, and Shikra CDSP and modem subsystems as applicable. - Add per-power-domain proxy performance states for Hawi CDSP and update Hawi, Maili, and SDX75 PAS compatible bindings and the SDX75 device tree. Correct the Qualcomm ADSP startup timeout. - Fetch auto-boot firmware only once and synchronize boot work with device removal. Bound ELF section header accesses, improve trace diagnostics, and update coredump configuration documentation. - Set 48-bit DMA masks for TI K3 DSP and R5 remote processors, correct mailbox message types, and enable compile testing for more TI drivers. Fix i.MX address range boundary checks and DSP runtime PM ordering, and simplify mailbox notification handling. - Harden Xilinx mailbox setup and teardown and avoid sending notifications when the transmit queue is full. Propagate STM32 optional IRQ lookup errors and correct the MediaTek MT8188 SCP register binding. * tag 'rproc-v7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (33 commits) remoteproc: qcom_q6v5_pas: Add QMI TMD cooling support for Shikra remoteproc: virtio: Remove stray white space remoteproc: virtio: Replace kmemdup with kmemdup_array remoteproc: virtio: Add vdev_to_rsc() helper remoteproc: core: Fetch the auto-boot firmware only once remoteproc: xlnx: fix typecast warnings remoteproc: qcom_q6v5_pas: enable QMI TMD cooling support remoteproc: qcom: pas: add support for TMD thermal cooling devices soc: qcom: Add QMI TMD support for remote thermal mitigation dt-bindings: remoteproc: qcom,pas: add #cooling-cells property remoteproc: qcom_q6v5_pas: add per-PD proxy performance states for Hawi CDSP dt-bindings: remoteproc: qcom,sm8550-pas: make qcom,hawi-cdsp-pas standalone arm64: dts: qcom: sdx75: Use SM8650 MPSS as fallback compatible dt-bindings: remoteproc: qcom,sm8550-pas: Make SDX75 MPSS fallback to SM8650 dt-bindings: remoteproc: qcom,sm8550-pas: Add Hawi and Maili MPSS as SM8650 fallback dt-bindings: remoteproc: Fix MT8188 SCP regs remoteproc: Use %p for pointer formatting remoteproc: Add compile testing for additional TI drivers remoteproc: k3-dsp: Fix usage of omap_mbox_message and mbox_msg_t remoteproc: k3: Include what we need and only what we need ...
12 daysMerge tag 'tty-7.4-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty / serial driver updates from Greg KH: "Here is the "big" set of tty and serial driver updates for 7.4-rc1. It's not really all that big, it's been kind of quiet in this area of the tree this development cycle in relation to other parts of the tree. But still, included in here are: - 8250 port updates and fixes - 8250 driver cleanups by Jiri - deletion of the obsolete moxa driver (making this pull request remove more lines than added!) - different serial driver updates for dma and other reported issues All of these have been in linux-next with no reported problems" * tag 'tty-7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (91 commits) tty: hvc: dcc: Detect JTAG connection only on CPU core 0 serial: earlycon: Use isdigit() in earlycon_init() serial: core: Use isdigit() in uart_parse_options() dt-bindings: serial: snps-dw-apb-uart: Add Synaptics sl2610 uart serial: amba-pl011: drive the bus during break in RS485 mode serial: mcf: update author email address serial: pmac_zilog: report received breaks serial: pmac_zilog: push received data to the port that received it serial: amba-pl011: keep transmitter enabled when disabling RS485 serial: ma35d1: Do not force-enable an unselected console serial: amba-pl011: honour delay_rts_before_send for every write Revert "serial: 8250_port: Drop duplicate NULL check" serial: 8250: make port operations work on struct uart_8250_port serial: 8250_omap: set priv->line before enabling the IRQ serial: 8250_lpss: do not touch uninitialized line in ehl_serial_exit() serial: 8250_exar: store the GPIO platform device in struct exar8250 serial: 8250_exar: remove useless void * casts serial: 8250: drop err label from serial8250_register_8250_port() serial: core: fix TIOCSSERIAL and TIOCSERCONFIG on uninitialised ports serial: max310x: don't transmit while an RS485 reconfigure is pending ...
13 daysMerge tag 'pci-v7.4-changes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Set supported_speeds in set_pcie_port_type() so sparc64 and powerpc, which call it via of_create_pci_dev() instead of the usual pci_setup_device(), correctly set the supported PCIe link speeds (Stian Halseth) - When pcie_set_mps() changes MPS, update the value in the saved state so a subsequent restore doesn't restore an invalid value (Niklas Cassel) - Skip Target Speed quirk on clamped ports with no link (Maciej W. Rozycki) Driver binding: - Assume control of portdrv-related features only when portdrv is enabled, since we can't use them without portdrv (Kuppuswamy Sathyanarayanan) - Centralize feature ownership checking so code only needs to check 'host->native_X' and doesn't need to also check 'pcie_ports_native' (Kuppuswamy Sathyanarayanan) Error handling: - Fix leaks when ACPI APEI/GHES error events overflow the kfifo or mention a device that no longer exists (Priyank Rathod) - Fix aer_process_err_devices() leak when a device is recorded as an error source purely by being mentioned in the Root Port Error Source and the device is inaccessible or logged only masked errors (Priyank Rathod) ASPM: - Disable ASPM when drivers request that, even if the OS doesn't own ASPM; otherwise drivers do it on their own, which is worse (Ilpo Järvinen) Power management: - Align hibernate poweroff flow with suspend flow for bridges so they can be powered down at hibernate as they are for suspend (Mario Limonciello) - Restore BARs after powering up during enumeration to fix a regression on devices that don't preserve state in D3hot (Keng-Yu Lin) - Avoid D3 on PLX PEX 8532/8533/8548 downstream ports, where putting them in D3hot takes down the whole switch (Imre Kaloz) Power control: - Add GPIO driver for Toshiba TC9563 embedded GPIO controller (Alex Elder) - Add DT documentation and pwrctrl driver support for TC9563 embedded GPIO controller (Lorenzo Bianconi) - Switch the tc9563 per-port reset to use the GPIO descriptor API instead of direct regmap accesses (Lorenzo Bianconi) - Only destroy devices created by pwrctrl core, so that when removing a PCIe controller driver that uses pwrctrl, we don't remove devices populated by another mechanism (Shawn Lin) - Power off child devices on power-on failure (Lorenzo Bianconi) PCIe native device hotplug: - Make the 'pciehp_poll_mode' parameter read-only to prevent changes via sysfs, which can cause errors when unbinding (Runyu Xiao) Virtualization: - Read SR-IOV VF Revision ID and Subsystem ID from VF instead of assuming they're the same as VF 0; they may differ (Logan Odell) - Add ACS quirk for Pericom PI7C9X2G304 switches (Hans de Goede) Peer-to-peer DMA: - Add Zhaoxin KX-6000, KH-40000, KX-6000G, KX-7000, and KH-50000 host bridges to allowlist (LeoLiu-oc) - Add Alibaba T-HEAD Yitian 710 host bridge to allowlist (Feng Tang) - Add Intel Haswell client host bridge to allowlist (Scott Lee) - Intel Xeon E3/E5/E7 0x6f00 host bridge to allowlist (kai zhang) - Fix handling of errors in pci_p2pdma_add_resource() to avoid (a) unmapping a BAR if registering another fails and (b) use after free of p2p_pgmap (Leon Romanovsky) - Wait for RCU readers before freeing state to avoid use-after-free of pdev->p2pdma (Leon Romanovsky) - Restrict pci_p2pmem_find_many() to providers backed by a pool (Leon Romanovsky) - Safely terminate ACS redirect lists to avoid out-of-bounds access to the buffer (Leon Romanovsky) - Silence 'Host bridge not in P2PDMA whitelist' warnings unless caller, e.g., pci_p2pmem_find_many(), requests 'verbose' (Leon Romanovsky) Sysfs: - Return -ENODEV or -EIO sysfs 'label' or 'acpi_index' attributes when Device Name _DSM fails, not -1, which is interpreted as -EPERM (Krzysztof Wilczyński) - Return valid sysfs 'acpi_index' attribute even if the Device Name _DSM returned an invalid 'label' (Krzysztof Wilczyński) - Expose sysfs 'acpi_index' and 'label' based on whether the Device Name _DSM returns valid data, not merely whether the _DSM is implemented (Krzysztof Wilczyński) - Avoid out-of-bounds reads of the label returned by the Device Name _DSM, which is in UTF-16 characters, not bytes (Krzysztof Wilczyński) - Reject unaligned resource I/O port accesses, which can oops on arm64 (Deepanshu Kartikey) Endpoint framework: - Pass the correct physical and virtual endpoint function numbers when setting translation of inbound memory windows (Koichiro Den) - Make embedded doorbell IRQ non-shared, since currently only the first EPF can allocate doorbells (Koichiro Den) - MSI doorbells currently target the first EPF attached to an EPC; let other EPFs try the embedded doorbell instead of failing when they can't use the MSI doorbell (Koichiro Den) - Serialize scan of vNTB virtual PCI bus with other PCI topology changes (Koichiro Den) - Manage vNTB lifetimes to avoid leaking virtual devices and buses and allow removal (Koichiro Den) - Track vNTB link state from both sides so both see the same effective link state (Koichiro Den) - Configure vNTB MSI-X when supported to avoid IOMMU faults and failure to deliver doorbell interrupts on RC (Koichiro Den) APM X-Gene PCIe controller driver: - Use devm for clocks so they're automatically disabled, unprepared, and released if errors happen during probe (Yuho Choi) ASPEED PCIe controller driver: - Fix clk and PHY leaks in aspeed_pcie_port_init() error paths (Liu Zhenlong) Broadcom iProc PCIe controller driver: - Expose devm_pci_alloc_host_bridge_release() so drivers can share a devm release function even if they don't need the device tree parsing done by devm_pci_alloc_host_bridge() (Bjorn Helgaas) - Request only the memory window from BCMA Enumeration ROM and warn if it doesn't match the one in DT, which fixes an iproc-bcma probe failure (Semih Baskan) Broadcom STB PCIe controller driver: - Replace bool properties for each SoC configuration with a u32 bitvector and a BFLAG() helper (Jim Quinlan) - Use a similar BQUIRK() helper to test various SoC quirks (Jim Quinlan) Cadence PCIe controller driver: - Remove device links to PHY, which are redundant because the PHY core itself adds them (Vladimir Oltean) - Return error (not success) from cdns_plat_pcie_probe() if pm_runtime_get_sync() or cdns_pcie_ep_setup() failed (Vladimir Oltean) - Correct the driver data pointer usage; previously .probe() stored 'struct cdns_plat_pcie *', but .shutdown() used the pointer as 'struct cdns_pcie *', resulting in accessing garbage (Linmao Li) ESWIN PCIe controller driver: - Publish the platform driver MODULE_DEVICE_TABLE so the driver can be autoloaded when built as a module (Pengpeng Hou) Freescale i.MX6 PCIe controller driver: - Fix resource and pwrctrl device leaks .probe() (Zhijian Han) - Improve i.MX95 Gen3 link stability by changing MPLLB_BANDWIDTH from default 120 to 140 (Richard Zhu) - Use dev_err_probe() in host init error path to silence -EPROBE_DEFER messages (Alexander Stein) - Avoid dereferencing NULL clock names when 'clocks' includes more phandles than 'clock-names' has names (Rudi Heitbaum) - Add suspend_poweroff flag so platforms like i.MX that power off RC controllers during suspend can enter L2 so endpoints can get PME_Turn_Off notifications before power loss (Richard Zhu) Freescale Layerscape PCIe controller driver: - Enable PROBE_PREFER_ASYNCHRONOUS to reduce probe time of the four controllers on LX2160A (Vincent Jardin) Intel VMD host bridge driver: - Flush DMA writes before handling MSI on Meteor Lake: MSI may arrive before write has completed, resulting in an nvme 30 second stall before a QID timeout and possibly other similar problems (Rickey Bartlett) - Flush DMA writes before handling MSI on Arrow Lake (Vladimir Nedoshivin) Marvell Aardvark PCIe controller driver: - Disable PHY on probe failures (Myeonghun Pak) Marvell MVEBU PCIe controller driver: - Refcount child OF nodes during .probe() to make a concurrent OF overlay removal safe (Krzysztof Kozlowski) MediaTek PCIe controller driver: - Find INTx DT property by 'interrupt-controller' name instead of assuming it's the first child node (Zhengping Zhang) MediaTek PCIe Gen3 controller driver: - Fix a 64-bit type truncation in mtk_pcie_set_trans_table() to avoid issues with windows above or larger than 4GB (Sreeraj S Kurup) NVIDIA Tegra264 PCIe controller driver: - Fix the Link Capabilities offset so we read the correct register (Bjorn Helgaas) Qualcomm PCIe controller driver: - Only collect reset GPIOs from PCI bridge DT nodes to avoid stealing resets used by downstream devices like USB controllers (Christopher Obbard) - Block accesses to downstream devices on link down to reduce a storm of Completion Timeout AER interrupts (Qiang Yu) - Skip system suspend/resume for firmware-managed PCIe, where firmware manages clocks, regulators, resets, etc (Mrinmay Sarkar) - Honor IOMMU provider's #iommu-cells in qcom_pcie_config_sid_1_9_0() (Manivannan Sadhasivam) - Deinitialize endpoint on remove (Guangshuo Li) - Treat Root Port error recovery as successful even if link doesn't come up after reset because the device was hot-unplugged (Konrad Dybcio) - Skip unnecessary iMSI-RX initialization if DT 'msi-map' is present, indicating an external MSI controller (Ayiluri Naga Rashmi) Renesas R-Car PCIe controller driver: - Limit Max_Read_Request_Size to 256 to avoid hardware erratum (Marek Vasut) - Support PERST# via reset subsystem as well as the existing GPIO support to prepare for R-Car Gen5 SoCs (Marek Vasut) - Add DT and driver support for the R-Car Gen 5 X5H (R8A78000) PCIe Gen 4 core (Marek Vasut) - Add Application/Local register reset DT description and driver support for both host and endpoint mode (Marek Vasut) - Add PM ops so controller works after suspend/resume (Marek Vasut) Renesas RZ/G3S PCIe controller driver: - Disable refclk on probe failure (Lad Prabhakar) - Propagate platform_get_irq_byname() errors so probe deferral works correctly (Lad Prabhakar) - Tear down INTx handlers if subsequent initialization fails (Lad Prabhakar) - Add RZ/G3L (R9A08G046) DT and driver support (Biju Das) Rockchip PCIe controller driver: - Limit host and endpoint controllers to 2.5 GT/s since 5.0 GT/s is unsafe per Rockchip (Geraldo Nascimento) Synopsys DesignWare PCIe controller driver: - Set DMA_BYPASS bit in outbound IATU CTRL2 register to avoid data corruption if the iATU translates DMA engine transactions (Sumit Kumar) - Use FIELD_PREP() to remove need for *_SHIFT definitions (Hans Zhang) TI DRA7xx PCIe controller driver: - Remove device links to PHY, which are redundant because the PHY core itself adds them (Vladimir Oltean) - Fix optional clock leak when .probe() fails by using devm_clk_get_optional_enabled() (Felix Gu) TI Keystone PCIe controller driver: - Remove device links to PHY, which are redundant because the PHY core itself adds them (Vladimir Oltean) UltraRISC PCIe controller driver: - Allow DWC drivers to skip outbound iATU setup if they don't need translation between CPU and PCI addresses (Xincheng Zhang) - Skip MEM outbound iATU setup on DP1000 (Xincheng Zhang) Xilinx Versal CPM PCIe controller driver: - Add DT and driver support for optional PERST# for use in warm reset scenarios (Sai Krishna Musham) Xilinx XDMA PCIe controller driver: - Fix device node reference leak in xilinx_pl_dma_pcie_init_irq_domain() (Wentao Liang)" * tag 'pci-v7.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (139 commits) PCI/pwrctrl: Power off child devices on power-on failure PCI/pwrctrl: Only destroy devices created by pwrctrl core PCI/pwrctrl: generic: Fix leaking array from of_regulator_bulk_get_all() PCI/pwrctrl: tc9563: Switch per-port reset to GPIO descriptor API PCI/pwrctrl: tc9563: Add GPIO auxiliary device support dt-bindings: PCI: toshiba,tc9563: Document embedded GPIO controller gpio: tc9563: Add support for the embedded GPIO controller PCI: qcom: Skip DWC MSI host initialization when DT 'msi-map' is present PCI: qcom: Ignore -ENODEV after Root Port reset PCI: qcom-ep: Deinitialize endpoint on remove PCI/sysfs: Reject unaligned resource I/O port accesses PCI: rcar-gen4: Add missing PM ops PCI: endpoint: pci-epf-vntb: Honor MSI-X selection PCI: endpoint: pci-epf-vntb: Use a local epf pointer in interrupt setup PCI: dwc: imx6: Use regmap_assign_bits() for conditional set/clear PCI: dwc: Describe DWC PCIe fields with full masks and FIELD_PREP() PCI: dwc: Rename pp->irq_domain to pp->msi_irq_domain PCI: dwc: Rename dw_pcie_allocate_domains() to dw_pcie_allocate_msi_domains() PCI: dwc: Correct PCIE_DW_PLAT_EP reference in Kconfig help PCI/ASPM: Disable ASPM when driver requests it ...
2026-10-22Merge tag 'soc-drivers-7.4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "There are lots of minor updates for driver subsystems managed through the soc tree (turris-omnia platform, cache driver, tee drivers, arm-cci, bus, memory) as well as soc vendor specific drivers (starfive, xilinx, microchip, nxp, amlogic, imx, renesas, samsung, ti, nvidia). The more notable changes are: - Larger updates for Qualcomm SoCs including support for SM8950 (Maili) SM8975 (Hawi), Glymur, Shikra, and IPQ5424 - Added SoC support for Exynos5515, Tegra264, Tegra410, R8A774A3, and MT8167 in existing drivers - Arm SCMI firmware driver support for ACPI PCC transport and module autoloading of protocol specific drivers - Apple crash log support for CrgA embedded controller" * tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (176 commits) platform: cznic: turris-omnia-mcu: stop button emulation producers cache: Make cpu_cache_invalidate_memregion() error out if there are no handlers soc: mpfs: use kref cleanup on probe failure arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port() bus: arm-cci: Drop CPU node reference in cci_ace_init_ports() soc: fsl: dpio: Free the IRQ before releasing the I/O object soc: fsl: dpio: Fix cleanup on IRQ registration failure bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr bus: fsl-mc: drop the fwnode links of the dpmacs nodes soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms() soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get() firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7 dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra firmware: qcom: tzmem: disable SHM bridge for SM7125 platform soc: qcom: ubwc: Add Kalambo UBWC config firmware: qcom: scm: Allow QSEECOM on Kalambo CRD ...
2026-10-21PCI/pwrctrl: tc9563: Switch per-port reset to GPIO descriptor APILorenzo Bianconi
Remove the local TC9563_GPIO_MASK and TC9563_GPIO_DEASSERT_BITS definitions, which are no longer used after switching to the GPIO descriptor API. Move TC9563_GPIO_CONFIG and TC9563_RESET_GPIO definitions in tc9563.h header file. Replace the direct regmap-based per-port reset logic in assert_deassert_reset() with gpiod_direction_output() calls, falling back to the legacy regmap approach only when no reset-gpios DT property is present for a given port. Add the reset GPIO pointer to struct tc9563_pwrctrl_cfg and introduce tc9563_pwrctrl_parse_reset_line() to look up reset-gpios from each PCI downstream port child node. The lookup is done lazily at the beginning of power_on(), returning -EPROBE_DEFER until the GPIO chip is registered. Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Alex Elder <elder@riscstar.com> Link: https://patch.msgid.link/20260909-pci-tc9563-aux-v5-4-c9b33f56c8d3@oss.qualcomm.com
2026-10-21gpio: tc9563: Add support for the embedded GPIO controllerAlex Elder
Add a driver for the GPIO controller embedded in the Toshiba TC9563 PCIe switch (and the Qualcomm QPS615). The device implements 37 GPIOs using two register banks: three registers control the first 32 GPIOs and three more control GPIOs 32-36. GPIOs 20 and 21 are reserved while GPIOs 22-24, 27-28, 31, and 34 are input-only. Register the driver as an auxiliary device driver. The TC9563 power controller creates the auxiliary device and provides a regmap that gives access to the GPIO registers, so use the gpio-regmap helpers to implement the GPIO chip. Signed-off-by: Alex Elder <elder@riscstar.com> Co-developed-by: Daniel Thompson <daniel@riscstar.com> Signed-off-by: Daniel Thompson <daniel@riscstar.com> Co-developed-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com> Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com> [bhelgaas: commit log per https://lore.kernel.org/arQ2mDjqHv4gmoOK@lore-desk] [bhelgaas: squash Geert Uytterhoeven <geert+renesas@glider.be> Kconfig fix: https://lore.kernel.org/all/45484c37512a3102495d8b75b6e9f72a141ba42e.1792574560.git.geert+renesas@glider.be, Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://patch.msgid.link/20260909-pci-tc9563-aux-v5-2-c9b33f56c8d3@oss.qualcomm.com
2026-10-05soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get()Somesh Dey
geni_icc_get() takes an icc_ddr string argument but never uses it: the DDR interconnect path is looked up with the "qup-memory" string literal directly, and the sole caller passes that same literal. The parameter carries no information. Drop the icc_ddr parameter and update the prototype and call site accordingly. Signed-off-by: Somesh Dey <somesh.dey@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260930-icc-ddr-param-remove-v1-1-61223714c9bc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-05soc: qcom: llcc: Add LLCC configuration for NordAnurag Pateriya
Add the sub-cache table for Nord, derived from the Nord AU (Safe IVI) SCT table and limited to the POR use cases that have a unique SCID and a usecase ID in llcc-qcom.h. Nord has the CFG0/CFG1 pairs and the full ALGO_ALLOC0..3 set, so it uses the v6 register offsets. num_banks is set explicitly because LLCC_LB_CNT in LLCC_COMMON_STATUS0 is four bits wide and cannot report sixteen banks; a wrong count makes the driver map a bank aperture in place of the broadcast region and abort on the first broadcast read. no_edac is set because the bootloader leaves the LLCC EDAC registers locked, as on Glymur. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Tested-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260910-nord_llcc-v1-2-30fd1cca65fe@oss.qualcomm.com Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
2026-10-05soc: qcom: ubwc: Add configuration for HawiWangao Wang
Add UBWC configuration data for the Hawi platform, which uses UBWC 7.0 and enables the required flags and highest bank bit settings. This allows drivers to query the correct UBWC capabilities on Hawi. Also add UBWC 7.0 support to the version tag helper so that qcom_ubwc_version_tag() returns the correct tag for UBWC 7.0. Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260812-ubwc_for_hawi_maili-v1-1-c29edecb3bd8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-09-25soc: qcom: Add QMI TMD support for remote thermal mitigationCasey Connolly
Add support for Qualcomm Messaging Interface (QMI) based Thermal Mitigation Device (TMD) cooling devices provided by remote subsystems. On Qualcomm platforms where remote processors expose mitigation controls through the TMD QMI service, client drivers need support to discover the service, register cooling devices for available mitigation endpoints, and forward cooling state updates to remote subsystems. Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Co-developed-by: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com> Co-developed-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260809-b4-qmi-tmd-v8-2-b15d47adc379@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-09-23soc: qcom: geni-se: Correct QUP Core ICC vote constantsViken Dadhaniya
The GENI_TO_CORE ("qup-core") ICC vote selects the QUP Core 2X clock rate. The CORE_2X_*_MHZ constants are expressed in Bps, but their values are several orders of magnitude too small. For example, the 50 MHz threshold is represented by 2500 rather than 25000000 Bps. As a result, clients using these constants can severely under-vote the QUP Core clock. Correct the constants to their intended Bps thresholds so that the ICC provider selects the corresponding QUP Core 2X clock rate. Fixes: 58ffbba6a399 ("soc: qcom: geni: Support for ICC voting") Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://patch.msgid.link/20260909-correct-icc-bandwidth-vote-constants-v1-1-fbebf6b3c341@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-09-23soc: qcom: geni-se: Correct QUP Core ICC vote constantsViken Dadhaniya
The GENI_TO_CORE ("qup-core") ICC vote selects the QUP Core 2X clock rate. The CORE_2X_*_MHZ constants are expressed in Bps, but their values are several orders of magnitude too small. For example, the 50 MHz threshold is represented by 2500 rather than 25000000 Bps. As a result, clients using these constants can severely under-vote the QUP Core clock. Correct the constants to their intended Bps thresholds so that the ICC provider selects the corresponding QUP Core 2X clock rate. Drop the unused definitions. Fixes: 58ffbba6a399 ("soc: qcom: geni: Support for ICC voting") Cc: stable@kernel.org Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260915-correct-icc-bandwidth-vote-constants-v2-1-f78eb611204e@oss.qualcomm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-08-31soc: qcom: apr: Drop unused apr_device_idUwe Kleine-König (The Capable Hub)
apr_device_id was introduced in commit 6adba21eb434 ("soc: qcom: Add APR bus driver") in 2018, and since then not a single driver made use of it. So drop the unused id_table pointer from struct apr_driver and move APR_NAME_SIZE to the apr header which still has a usage of it. Note that with the id_table being NULL apr_device_match() degrades to just of_driver_match_device(), so replace this callback accordingly. Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/e8b352f33ae38df3616dc157c1cafd13d49c5e3e.1784554037.git.u.kleine-koenig@baylibre.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-08-31soc: qcom: llcc: Update the SCT table for IPQ5424Kathiravan Thirumoorthy
Update the IPQ5424 LLCC slice configuration table to give the PPE and Wi-Fi datapaths dedicated slices. Assign slice IDs 1 and 5 to the PPE RX descriptor and RX fill use cases, slice IDs 6 and 7 to the Wi-Fi radios connected over PCIe, and slice ID 2 to the CPU subsystem. Adjust the corresponding capacities, priorities, and way masks for these consumers. These slice assignments are based on recommendations from the performance team, following throughput measurements on IPQ5424. Having the dedicated slice configuration for each of these use cases helps to improve the networking throughput by more than 1 Gbps. Rename the usecase IDs for slice IDs 1 and 2 because LLCC_CPUSS and LLCC_VIDSC0 do not describe the actual users of those slices. Assisted-by: LLM Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260819-ipq5424_llcc_updates-v3-1-42b48451481d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-08-25Merge tag 'rproc-v7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux Pull remoteproc updates from Bjorn Andersson: "Add a remoteproc driver and binding for AMD MicroBlaze/V soft cores executing from dual-port BRAM, with clock and reset control and support for firmware without a resource table. Introduce a generic Qualcomm PAS service with SCM and OP-TEE backends, and migrate the PAS, MSS, and WCNSS remoteproc drivers to it. Add Nord ADSP and CDSP support, Eliza CDSP support, Maili ADSP/CDSP bindings, and late-attach SoCCP support for Kaanapali, Hawi, Maili, and Glymur. Enable BAM-DMUX child devices for PAS modems and fix PAS memory protection, handover, shutdown, and resource lifetime handling. Harden remoteproc lifecycle handling by attaching asynchronously, stopping crashed processors, synchronizing crash work with removal, and forcing shutdown before device resources are released. Reallocate resources during attach recovery and fix several reference and error-path leaks. Add Xilinx R5 crash detection and move RPU start and stop sequencing into the platform firmware driver. Consolidate write-combining carveout mapping callbacks, use correct I/O-memory accessors, and share optional ELF resource-table handling across drivers. Convert the TI Wakeup M3 binding to DT schema, correct Qualcomm and generic remoteproc bindings, and harden resource-table iteration against signed-offset out-of-bounds accesses" * tag 'rproc-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (60 commits) remoteproc: fix OOB read via signed offset in rsc_table_for_each_entry() remoteproc: replace BSD blurb with SPDX identifier in rsc_table.h remoteproc: replace BSD blurb with SPDX identifier in remoteproc.h remoteproc: fix coding style issues in remoteproc.h MAINTAINERS: add rsc_table.h to remoteproc entry remoteproc: qcom: pas: Add Nord ADSP and CDSP support dt-bindings: remoteproc: qcom,nord-pas: Document Nord PAS remoteproc: qcom: pas: Drop unused dtb_mem_region field remoteproc: qcom: pas: Map/unmap subsystem region before auth_and_reset remoteproc: qcom: pas: Fix the PAS context creation placement remoteproc: qcom: pas: Guard dtb metadata release with dtb_pas_id check remoteproc: qcom: annotate mem_region fields with __iomem arm64: dts: qcom: eliza: Add fallback compatible for ADSP remoteproc dt-bindings: remoteproc: qcom,milos-pas: Move Eliza ADSP to SM8550 schema remoteproc: qcom: pas: Add Eliza CDSP support dt-bindings: remoteproc: qcom,sm8550-pas: Add Eliza CDSP compatible remoteproc: qcom: q6v5: Request shutdown if crash is triggered host-side remoteproc: Force shutdown during device removal remoteproc: Prevent crash handling to race with rproc_del() remoteproc: Allow shutdown of crashed processors ...
2026-08-19Merge tag 'spi-v7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "Along with a lot of driver specific work we've got a couple of core features here. The bigger one is that we've now got support for instantiating devices from sysfs similarly to how it's already done for I2C, this is used with development boards with non-enumerable expansion headers since SPI devices need to be manually specified. We also have support for the DQS signal on higher end flash devices. - Support for instantiating devices from sysfs, useful for development boards with non-enumerable plugin modules, from Vishwaroop A. - Support for DQS in spi-mem, an additional signal used by flash devices to avoid clock skew from Miquel Raynal. - Support for more advanced SPI modes on DesignWare controllers from Sudip Mukherjee. - Changes from Jisheng Zhang to update to modern methods of specifying the PM callbacks. - Fixes for DMA mapping error handling, plus KUnit tests for this, from Honghui Jiang. - Substantial cleanup and performance work in the nxp-spi driver. - Support for Microchip LAN969x, Nuvoton MA35D1 QSPI, Qualcomm SA8255p and SA8797P, and StarFive JHB100 SFC" * tag 'spi-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (132 commits) spi: Add KUnit coverage for DMA mapping error paths spi: Clear current DMA devices when unmapping a message spi: Move __spi_unmap_msg() before __spi_map_msg() spi: Fix DMA mapping ownership on partial map failure spi: dt-bindings: sun6i: Add compatibles for A733's SPI controllers spi: ma35d1-qspi: Use the existing update helper spi: ma35d1-qspi: Add DTR support spi: ma35d1-qspi: Allow several command bytes spi: ma35d1-qspi: Move speed setting to bus configuration spi: ma35d1-qspi: Remove redundant reset operation spi: dw: Remove shadowed dws in dw_spi_setup() spi: img-spfi: don't disable runtime PM on DMA deferred probe spi: mtk-nor: Propagate errors from IRQ request spi: mtk-nor: Propagate errors from optional IRQ lookup spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b spi: spi-qpic-snand: add quad mode support spi: spi-qpic-snand: move command mapping helper spi: hisi-sfc-v3xx: Propagate errors from optional IRQ lookup spi: meson-spifc: use devm_pm_runtime_set_active_enabled spi: sprd-adi: Fix probe succeeding without registering the controller ...
2026-08-18soc: qcom: ubwc: Fix missing includeDaniel Baluta
When CONFIG_QCOM_UBWC_CONFIG=n, compiler needs to know the definition of ERR_PTR otherwise there will be a compilation error: In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c:7: ./include/linux/soc/qcom/ubwc.h: In function ‘qcom_ubwc_config_get_data’: ./include/linux/soc/qcom/ubwc.h:45:16: error: implicit declaration of function ‘ERR_PTR’ [-Wimplicit-function-declaration] Fix this by including <linux/err.h> Fixes: 1924272b9ce1 ("soc: qcom: Add UBWC config provider") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Tested-by: Nathan Chancellor <nathan@kernel.org> # build Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-08-10Merge tag 'qcom-drivers-for-7.3-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers More Qualcomm driver updates for v7.3 Add SMEM parsing for DDR configuration data and use its highest bank address bit to select the appropriate UBWC configuration. Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers. Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16. Correct GENI firmware-size validation using the hardware CFG RAM depth and correct the PMIC GLINK Thunderbolt extradata layout. Document the Nord AOSS side channel and the IMEM minidump SRAM property. Clean up Qualcomm statistics macros and the WCNSS binding schema. * tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: media: qcom: Switch to generic PAS TZ APIs dt-bindings: soc: qcom,aoss-qmp: Document Nord AOSS side channel dt-bindings: sram: qcom,imem: Add minidump-sram pattern property soc: qcom: qcom_stats: Replace CLIENT_VOTES_OFFSET macro with sizeof() soc: qcom: qcom_stats: Remove unused macro definitions soc: qcom: ubwc: Get HBB from SMEM soc: qcom: smem: Expose DDR data from SMEM soc: qcom: smem: Use 'unsigned int' instead of 'unsigned' firmware: qcom: scm: Fix tzmem state on probe retry firmware: qcom: scm: Fix reserved memory cleanup on probe failure firmware: qcom: scm: Fix NULL dereference in IRQ handler before __scm is published firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A16 (UX3607OA) soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware size soc: qcom: pmic_glink_altmode: Define the TBT extradata properly dt-bindings: soc: qcom,wcnss: Drop redundant $ref of firmware-name property Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-08-04Merge tag 'qcom-drivers-for-7.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.3 Add Maili platform bindings for SCM, IMEM, AOSS, and PMIC GLINK. Add Shikra IMEM, RPM SMD, LLCC, and UBWC support, including handling for firmware-configured LLCC ECC interrupts. Add the generic Peripheral Authentication Service with SCM and OP-TEE backends, and migrate the MSM DRM and IPA drivers to it. Add SCM SMC-call tracepoints and configurable minidump delivery through always-on SRAM. Correct SCM download-mode pointer ordering and improve download-mode probe diagnostics. Rework the UBWC configuration database and add Milos and Shikra configuration. Add protection-domain mappings for SA8775P and QCS8300, support newer ICE versions, Hawi subsystem statistics, and SDM850 identification. Simplify Qualcomm SoC Kconfig selection and architecture dependencies. Use managed resources in EBI2 and RPMh RSC probe paths to correct cleanup on failures. * tag 'qcom-drivers-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (44 commits) soc: qcom: llcc: Skip ECC interrupt setup on Shikra, pre-configured by DSF dt-bindings: sram: Document qcom,shikra-imem compatible net: ipa: Switch to generic PAS TZ APIs firmware: qcom: scm: Add minidump SRAM support firmware: qcom: scm: use dev_err_probe() for dload address failure firmware: qcom: scm: Fix missing smp_load_acquire() dt-bindings: firmware: qcom,scm: Add minidump SRAM property drm/msm: Switch to generic PAS TZ APIs bus: qcom-ebi2: use managed resources for clocks and children soc: qcom: rpmh-rsc: manage PM notifiers with devres firmware: qcom: scm: Allow QSEECOM on Honor Magicbook Art 14 firmware: qcom: scm: instrument SMC call path with tracepoints firmware: qcom: scm: add trace events for the SMC call interface soc: qcom: Avoid SCM and SPM for cpuidle drivers soc: qcom: Make important drivers default soc: qcom: Restrict drivers per ARM/ARM64 soc: qcom: Hide all drivers behind selectable menu MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service firmware: qcom: Add a PAS TEE service firmware: qcom_scm: Migrate to generic PAS service ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-30remoteproc: qcom: pas: Map/unmap subsystem region before auth_and_resetMukesh Ojha
Qualcomm remoteproc drivers such as qcom_q6v5_mss, which do not use the Peripheral Authentication Service (PAS), always map the MBA region before use and unmap it once the usage is complete. This behavior was introduced to avoid issues seen in the past where speculative accesses from the application processor to the MBA region after it was assigned to the remote Q6 led to an XPU violation. The issue was mitigated by unmapping the region before handing control to the remote Q6. Currently, most Qualcomm SoCs using the PAS driver run either with a standalone QHEE or the Gunyah hypervisor. In these environments, the hypervisor unmaps the Q6 memory from HLOS Stage-2 and remaps it into the Q6 Stage-2 page table. As a result, speculative accesses from HLOS cannot reach the region even if it remains mapped in HLOS Stage-1; therefore, XPU violations cannot occur. However, when the same SoC runs Linux at EL2, Linux itself must perform the unmapping to avoid such issues. It is still correct to apply this mapping/ unmapping sequence even for SoCs that run under Gunyah, so this behavior should not be conditional. Introduce qcom_pas_ctx_map() in qcom_pas.h to centralise the ioremap_wc pattern used by both qcom_q6v5_pas and qcom_mdt_pas_load, and use it in both places. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724182858.1868271-5-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30soc: qcom: smem: Expose DDR data from SMEMKonrad Dybcio
Most modern Qualcomm platforms (>= SM8150) expose information about the DDR memory present on the system via SMEM. Details from this information is used in various scenarios, such as multimedia drivers configuring the hardware based on the "Highest Bank address Bit" (hbb), or the list of valid frequencies in validation scenarios... Add support for parsing v3-v7 version of the structs. Unforunately, they are not versioned, so some elbow grease is necessary to determine which one is present. See for reference: ver 3: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/1d11897d2cfcc7b85f28ff74c445018dbbecac7a ver 4: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/f6e9aa549260bbc0bdcb156c2b05f48dc5963203 ver 5: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/617d3297abe8b1b8dd3de3d1dd69c3961e6f343f ver 5 with 6regions: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/d770e009f9bae58d56d926f7490bbfb45af8341f ver 6: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/62659b557fdb1551b20fae8073d1d701dfa8a62e ver 7: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/734d95599c5ebb1ca0d4e1639142e65c590532b7 Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://git.codelinaro.org/clo/la/abl/tianocore/edk2/-/commit/1d11897d2cfcc7b85f28ff74c445018dbbecac7a Link: https://lore.kernel.org/r/20260727-topic-smem_dramc-v5-2-66188b3e338d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware sizeViken Dadhaniya
The hardcoded MAX_GENI_CFG_RAMn_CNT limit is not accurate for all SoCs: some targets have less CFG RAM than the constant implies, while others like QCS615 need more entries than the old limit of 455 allowed, causing valid firmware to be rejected at load time. Rather than hardcoding a constant, read PROG_RAM_DEPTH from SE_HW_PARAM_2 at runtime to get the actual CFG RAM depth of the hardware instance and use that as the upper bound for firmware size validation. Fixes: d4bf06592ad6 ("soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem") Cc: stable@vger.kernel.org Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702-qup-se-increase-ram-cnt-v3-1-80b363373a5b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-29soc: qcom: geni-se: trace: Add trace event support for GENI SE registers dumpPraveen Talari
Diagnosing GENI SE-based driver (serial, SPI, I2C) failures currently requires reading each hardware register individually, either through ad hoc debug code or a debugger. This is slow, requires the state to remain stable across the multiple reads, and cannot be run non-intrusively during normal operation without adding printk-style noise to each driver. Add a new trace event header for the Qualcomm GENI Serial Engine (SE) framework providing a geni_se_regs tracepoint. This tracepoint captures a comprehensive snapshot of the GENI SE hardware state in a single trace record, making it possible to correlate register values at a precise point in time without multiple sequential reads. The trace event records the following register groups: - Main/secondary command and IRQ status (M_CMD0, S_CMD0, M/S_IRQ_STATUS) - Engine status, IOS, and command control/error registers - TX/RX FIFO status and watermark registers (including RFR watermark) - M/S GP length registers - DMA TX/RX IRQ, enable, length, pointer, attribute, and burst registers - DMA interface enable, general config, QSB trans config, and debug - M/S IRQ enable, GSI event enable, and top-level SE IRQ enable - Serial master/slave clock config, general config, output control, clock control RO, FIFO interface disable, and FW multilock MSA - Clock select register Having all these registers captured atomically in a single ftrace record allows drivers built on top of the GENI SE framework (serial, SPI, I2C) to invoke this tracepoint on error paths and reconstruct the full engine state during post-mortem analysis without instrumenting each driver separately. Acked-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Link: https://patch.msgid.link/20260729-add-tracepoints-for-se-reg-dump-v4-1-08bbd63b0ed2@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2026-07-09remoteproc: qcom_q6v5_pas: Switch over to generic PAS TZ APIsSumit Garg
Switch qcom_q6v5_pas client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Since qcom_q6v5_pas depends on MDT loader for PAS firmware loading, it has to be switched over to generic PAS APIs in this commit to avoid any build issues. Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Tested-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> # Lemans Tested-by: Vignesh Viswanathan <vignesh.viswanathan@oss.qualcomm.com> # IPQ9650 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702115835.167602-5-sumit.garg@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-05soc: qcom: ubwc: sort out the rest of the UBWC swizzle settingsDmitry Baryshkov
Sort out the remaining UBWC swizzle values, using flags to control whether level 2 and level 3 swizzling are enabled or not. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-27-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-05soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0Dmitry Baryshkov
UBWC devices before 4.0 use standard UBWC swizzle levels. As all the drivers now use the qcom_ubwc_swizzle() helper, move those values to the helper, leaving UBWC 4.0+ intact for now. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-26-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-05soc: qcom: ubwc: drop macrotile_mode from the databaseDmitry Baryshkov
All the users have been migrated to using qcom_ubwc_macrotile_mode() instead of reading the raw value from the config structure. Drop the field from struct qcom_ubwc_cfg_data and replace it with the calculated value. Split single UBWC_3_0 into UBWC_3_0 (no macrotile mode) and UBWC_3_1 (with macrotile mode). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-25-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-05soc: qcom: ubwc: drop ubwc_bank_spreadDmitry Baryshkov
According to the documentation, UBWC bank spreading should be enabled for all targets. It's just not all targets have separate bit to control it. Drop the bit from the database and make the helper always return true. If we need to change it later, the helper can be adjusted according to the programming guides. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-24-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-05soc: qcom: ubwc: drop ubwc_dec_versionDmitry Baryshkov
The ubwc_dec_version field has been inherited from the MDSS driver and it is equal to the version of the UBWC decoder in the display block only. Other IP Cores can have different UBWC decoders and so the version would vary between blocks. As the value is no longer used as is not relevant to other UBWC database consumers, drop it from the UBWC database. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-23-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-05soc: qcom: ubwc: set min_acc length to 64 for all UBWC 1.0 targetsDmitry Baryshkov
According to the documentation, the MAL should be set for all UBWC 1.0 targets, no matter what is the version of the UBWC decoders are present on the device. The helper comes from DPU / GPU world, where there was no separate bit to control MAL before UBWC 2.0. As the helper is now being used by other drivers too, correct the helper to return the correct MAL value (Iris doesn't support UBWC 1.0 devices for now, so there is no changes of the behaviour). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-22-72f2749bc807@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-03Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> ↵Uwe Kleine-König (The Capable Hub)
(headers) <linux/mod_devicetable.h> is included in a many files: $ git grep '<linux/mod_devicetable.h>' ef0c9f75a195 | wc -l 1598 ; some of them are widely used headers. To stop mixing up different and unrelated driver( type)s let the subsystem headers only use the subset of the recently split <linux/mod_devicetable.h> that are relevant for them. The fallout (I hope) is addressed in the previous commits that handle sources relying on e.g. <linux/i2c.h> pulling in the full legacy header and thus providing pci_device_id. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Link: https://patch.msgid.link/199fe46b624ba07fb9bd3e0cd6ff13757932cb5f.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
2026-05-21Merge branch '20260227061544.1785978-1-praveen.talari@oss.qualcomm.com' into ↵Bjorn Andersson
drivers-for-7.2 Merge the refactoring and helper functions in the Qualcomm GENI Serial Engine driver through a topic branch. These changes will provide the ability to add support managing power and performance for the GENI instances in platforms where these are controlled as SCMI resources. The patches are merged through a topic branch to avoid conflicts with other changes, while making them available to other subsystems. Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21soc: qcom: geni-se: Introduce helper APIs for performance controlPraveen Talari
The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently manage performance levels and operating points directly. This resulting in code duplication across drivers. such as configuring a specific level or find and apply an OPP based on a clock frequency. Introduce two new helper APIs, geni_se_set_perf_level() and geni_se_set_perf_opp(), addresses this issue by providing a streamlined method for the GENI Serial Engine (SE) drivers to find and set the OPP based on the desired performance level, thereby eliminating redundancy. Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20260227061544.1785978-8-praveen.talari@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21soc: qcom: geni-se: Introduce helper API for attaching power domainsPraveen Talari
The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle the attachment of power domains. This often leads to duplicated code logic across different driver probe functions. Introduce a new helper API, geni_se_domain_attach(), to centralize the logic for attaching "power" and "perf" domains to the GENI SE device. Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20260227061544.1785978-7-praveen.talari@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21soc: qcom: geni-se: Add resources activation/deactivation helpersPraveen Talari
The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource activation/deactivation sequences independently, leading to code duplication. Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to power on/off resources.The activate function enables ICC, clocks, and TLMM whereas the deactivate function disables resources in reverse order including OPP rate reset, clocks, ICC and TLMM. Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20260227061544.1785978-6-praveen.talari@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21soc: qcom: geni-se: Introduce helper API for resource initializationPraveen Talari
The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate code for initializing shared resources such as clocks and interconnect paths. Introduce a new helper API, geni_se_resources_init(), to centralize this initialization logic, improving modularity and simplifying the probe function. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20260227061544.1785978-4-praveen.talari@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21soc: qcom: geni-se: Add geni_icc_set_bw_ab() functionPraveen Talari
Add a new function geni_icc_set_bw_ab() that allows callers to set average bandwidth values for all ICC (Interconnect) paths in a single call. This function takes separate parameters for core, config, and DDR average bandwidth values and applies them to the respective ICC paths. This provides a more convenient API for drivers that need to configure specific average bandwidth values. Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20260227061544.1785978-3-praveen.talari@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-19Merge branch '20260507-ubwc-rework-v4-4-c19593d20c1d@oss.qualcomm.com' into ↵Bjorn Andersson
drivers-for-7.2 Merge the initial set of UBWC rework through a topic branch, to allow it being shared with the DRM/MSM branch for the continuation.
2026-05-19soc: qcom: ubwc: add helper controlling AMSBC enablementDmitry Baryshkov
Adreno and MDSS drivers need to know whether to enable AMSBC. Add separate helper, describing that feature. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-4-c19593d20c1d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-19soc: qcom: ubwc: define helper for MDSS and Adreno driversDmitry Baryshkov
Define special helper returning version setting for MDSS and A8xx drivers. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-3-c19593d20c1d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-19soc: qcom: ubwc: define UBWC 3.1Dmitry Baryshkov
Follow the comment for the macrotile_mode and introduce separate revision for UBWC 3.0 + 8-channel macrotiling mode. It is not used by the database (since the drivers are not yet changed to handle it yet). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-2-c19593d20c1d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13soc: qcom: llcc-qcom: Capitalize LLCC/EDAC in comments and diagnosticsFrancisco Munoz Ruiz
Capitalize occurrences of the acronym "LLCC" and "EDAC" in comments and diagnostic text to improve consistency and readability. Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-3-b5017ce2020b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13soc: qcom: llcc-qcom: get SCT descriptors from fw-populated memoryFrancisco Munoz Ruiz
Retrieve System Cache Table (SCT) descriptors from a shared memory region populated by firmware. SCT initialization and programming are performed entirely by firmware outside of Linux. The LLCC driver only consumes the pre-initialized descriptor data and does not configure SCT itself. Support this mechanism for future SoCs that provide SCT programming via firmware. Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-2-b5017ce2020b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-17Merge tag 'rpmsg-v7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux Pull rpmsg updates from Bjorn Andersson: "Mark 'data' argument in rpmsg_send() const, and perculate to related drivers. Replace deprecated class_destroy() with class_unregister()" * tag 'rpmsg-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: media: platform: mtk-mdp3: Constify buffer passed to mdp_vpu_sendmsg() ASoC: qcom: Constify GPR packet being send over GPR interface rpmsg: Constify buffer passed to send API remoteproc: mtk_scp: Constify buffer passed to scp_send_ipi() remoteproc: mtk_scp_ipi: Constify buffer passed to scp_ipi_send() drivers: rpmsg: class_destroy() is deprecated
2026-04-16Merge tag 'soc-drivers-7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ...
2026-04-06ASoC: qcom: Constify GPR packet being send over GPR interfaceKrzysztof Kozlowski
gpr_send_pkt() and pkt_router_send_svc_pkt() only send the GPR packet they receive, without any need to actually modify it, so mark the pointer to GPR packet as pointer to const for code safety and code self-documentation. Several users of this interface can follow up and also operate on pointer to const. Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260317-rpmsg-send-const-v3-4-4d7fd27f037f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30Merge branch '20260125-iris-ubwc-v4-1-1ff30644ac81@oss.qualcomm.com' into ↵Bjorn Andersson
drivers-for-7.1 Merge the new helpers in UBWC driver through a topic branch, to allow them to be shared with display and video branches as well.
2026-03-30soc: qcom: ubwc: add helpers to get programmable valuesDmitry Baryshkov
Currently the database stores macrotile_mode in the data. However it can be derived from the rest of the data: it should be used for UBWC encoding >= 3.0 except for several corner cases (SM8150 and SC8180X). The ubwc_bank_spread field seems to be based on the impreside data we had for the MDSS and DPU programming. In some cases UBWC engine inside the display controller doesn't need to program it, although bank spread is to be enabled. Bank swizzle is also currently stored as is, but it is almost standard (banks 1-3 for UBWC 1.0 and 2-3 for other versions), the only exception being Lemans (it uses only bank 3). Add helpers returning values from the config for now. They will be rewritten later, in a separate series, but having the helper now simplifies refacroring the code later. Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260125-iris-ubwc-v4-2-1ff30644ac81@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30soc: qcom: ubwc: add helper to get min_acc lengthDmitry Baryshkov
MDSS and GPU drivers use different approaches to get min_acc length. Add helper function that can be used by all the drivers. The helper reflects our current best guess, it blindly copies the approach adopted by the MDSS drivers and it matches current values selected by the GPU driver. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260125-iris-ubwc-v4-1-1ff30644ac81@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-15Merge branch '20260309230346.3584252-2-daniel.lezcano@oss.qualcomm.com' into ↵Bjorn Andersson
drivers-for-7.1 Merge the relocated constants through a topic branch, to allow this change being shared with other trees.
generated by cgit v1.2.3 (git 2.0.4) at 2026-11-05 21:07:35 +0000