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|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe controller on MediaTek SoCs
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
properties:
compatible:
oneOf:
- enum:
- airoha,an7583-pcie
- mediatek,mt2712-pcie
- mediatek,mt7622-pcie
- mediatek,mt7629-pcie
- items:
- const: airoha,en7523-pcie
- const: mediatek,mt7622-pcie
reg:
maxItems: 1
reg-names:
enum: [ port0, port1 ]
clocks:
minItems: 1
maxItems: 6
clock-names:
minItems: 1
items:
- enum: [ sys_ck0, sys_ck1 ]
- enum: [ ahb_ck0, ahb_ck1 ]
- enum: [ aux_ck0, aux_ck1 ]
- enum: [ axi_ck0, axi_ck1 ]
- enum: [ obff_ck0, obff_ck1 ]
- enum: [ pipe_ck0, pipe_ck1 ]
resets:
maxItems: 1
reset-names:
const: pcie-rst1
interrupts:
maxItems: 1
interrupt-names:
const: pcie_irq
phys:
maxItems: 1
phy-names:
enum: [ pcie-phy0, pcie-phy1 ]
power-domains:
maxItems: 1
mediatek,pbus-csr:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to pbus-csr syscon
- description: offset of pbus-csr base address register
- description: offset of pbus-csr base address mask register
description:
Phandle with two arguments to the syscon node used to detect if
a given address is accessible on PCIe controller.
'#interrupt-cells':
const: 1
interrupt-controller:
description: Interrupt controller node for handling legacy PCI interrupts.
type: object
properties:
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
interrupt-controller: true
required:
- '#address-cells'
- '#interrupt-cells'
- interrupt-controller
additionalProperties: false
required:
- compatible
- reg
- reg-names
- ranges
- clocks
- clock-names
- '#interrupt-cells'
- interrupts
- interrupt-names
- interrupt-controller
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:
const: airoha,an7583-pcie
then:
properties:
reg-names:
const: port1
clocks:
maxItems: 1
clock-names:
const: sys_ck1
phy-names:
const: pcie-phy1
power-domain: false
required:
- resets
- reset-names
- phys
- phy-names
- mediatek,pbus-csr
- if:
properties:
compatible:
const: mediatek,mt2712-pcie
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
minItems: 2
maxItems: 2
reset: false
reset-names: false
power-domains: false
mediatek,pbus-csr: false
required:
- phys
- phy-names
- if:
properties:
compatible:
const: mediatek,mt7622-pcie
then:
properties:
clocks:
minItems: 6
reset: false
reset-names: false
phys: false
phy-names: false
mediatek,pbus-csr: false
required:
- power-domains
- if:
properties:
compatible:
const: mediatek,mt7629-pcie
then:
properties:
clocks:
minItems: 6
reset: false
reset-names: false
mediatek,pbus-csr: false
required:
- power-domains
- if:
properties:
compatible:
contains:
const: airoha,en7523-pcie
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
reset: false
reset-names: false
phys: false
phy-names: false
power-domain: false
mediatek,pbus-csr: false
unevaluatedProperties: false
examples:
# MT2712
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
soc_1 {
#address-cells = <2>;
#size-cells = <2>;
pcie@112ff000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
reg = <0 0x112ff000 0 0x1000>;
reg-names = "port1";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie_irq";
clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */
<&pericfg>; /* CLK_PERI_PCIE1 */
clock-names = "sys_ck1", "ahb_ck1";
phys = <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy1";
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie@11700000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
reg = <0 0x11700000 0 0x1000>;
reg-names = "port0";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie_irq";
clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */
<&pericfg>; /* CLK_PERI_PCIE0 */
clock-names = "sys_ck0", "ahb_ck0";
phys = <&u3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy0";
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
# MT7622
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt7622-power.h>
soc_2 {
#address-cells = <2>;
#size-cells = <2>;
pcie@1a143000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
reg = <0 0x1a143000 0 0x1000>;
reg-names = "port0";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "pcie_irq";
clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */
<&pciesys>, /* CLK_PCIE_P0_AHB_EN */
<&pciesys>, /* CLK_PCIE_P0_AUX_EN */
<&pciesys>, /* CLK_PCIE_P0_AXI_EN */
<&pciesys>, /* CLK_PCIE_P0_OBFF_EN */
<&pciesys>; /* CLK_PCIE_P0_PIPE_EN */
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
"axi_ck0", "obff_ck0", "pipe_ck0";
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0_1 0>,
<0 0 0 2 &pcie_intc0_1 1>,
<0 0 0 3 &pcie_intc0_1 2>,
<0 0 0 4 &pcie_intc0_1 3>;
pcie_intc0_1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie@1a145000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
reg = <0 0x1a145000 0 0x1000>;
reg-names = "port1";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "pcie_irq";
clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */
/* designer has connect RC1 with p0_ahb clock */
<&pciesys>, /* CLK_PCIE_P0_AHB_EN */
<&pciesys>, /* CLK_PCIE_P1_AUX_EN */
<&pciesys>, /* CLK_PCIE_P1_AXI_EN */
<&pciesys>, /* CLK_PCIE_P1_OBFF_EN */
<&pciesys>; /* CLK_PCIE_P1_PIPE_EN */
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
"axi_ck1", "obff_ck1", "pipe_ck1";
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1_1 0>,
<0 0 0 2 &pcie_intc1_1 1>,
<0 0 0 3 &pcie_intc1_1 2>,
<0 0 0 4 &pcie_intc1_1 3>;
pcie_intc1_1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
# AN7583
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
soc_3 {
#address-cells = <2>;
#size-cells = <2>;
pcie@1fa92000 {
compatible = "airoha,an7583-pcie";
device_type = "pci";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fa92000 0x0 0x1670>;
reg-names = "port1";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys_ck1";
phys = <&pciephy>;
phy-names = "pcie-phy1";
ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
resets = <&scuclk>; /* AN7583_PCIE1_RST */
reset-names = "pcie-rst1";
mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie_irq";
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1_4: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
|
