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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDX55 PCI Express Root Complex
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Manivannan Sadhasivam <mani@kernel.org>
properties:
compatible:
enum:
- qcom,pcie-sdx55
reg:
minItems: 5
maxItems: 6
reg-names:
minItems: 5
items:
- const: parf
- const: dbi
- const: elbi
- const: atu
- const: config
- const: mhi
clocks:
maxItems: 7
clock-names:
items:
- const: pipe
- const: aux
- const: cfg
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a
- const: sleep
interrupts:
maxItems: 8
interrupt-names:
items:
- const: msi
- const: msi2
- const: msi3
- const: msi4
- const: msi5
- const: msi6
- const: msi7
- const: msi8
resets:
maxItems: 1
reset-names:
items:
- const: pci
required:
- power-domains
- resets
- reset-names
allOf:
- $ref: qcom,pcie-common.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie@1c00000 {
compatible = "qcom,pcie-sdx55";
reg = <0x01c00000 0x3000>,
<0x40000000 0xf1d>,
<0x40000f20 0xc8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config";
ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"msi8";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
<&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"sleep";
assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
<0x100 &apps_smmu 0x0201 0x1>,
<0x200 &apps_smmu 0x0202 0x1>,
<0x300 &apps_smmu 0x0203 0x1>,
<0x400 &apps_smmu 0x0204 0x1>;
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_phy>;
phy-names = "pciephy";
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "pci";
perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
|
