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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2025, Google LLC
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Tensor Series G5 (Laguna) USB PHY
maintainers:
- Roy Luo <royluo@google.com>
description:
Describes the USB PHY interfaces integrated with the DWC3 USB controller on
Google Tensor SoCs, starting with the G5 generation (laguna).
Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
and USB3.2/DisplayPort combo PHY IP.
properties:
compatible:
const: google,lga-usb-phy
reg:
items:
- description: USB3.2/DisplayPort combo PHY core registers.
- description: USB3.2/DisplayPort combo PHY Type-C Assist registers.
- description: eUSB 2.0 PHY core registers.
- description: Top-level wrapper registers for the integrated PHYs.
reg-names:
items:
- const: usb3_core
- const: usb3_tca
- const: usb2_core
- const: usbdp_top
"#phy-cells":
description: |
The phandle's argument in the PHY specifier selects one of the three
following PHY interfaces.
- 0 for USB high-speed.
- 1 for USB super-speed.
- 2 for DisplayPort.
const: 1
clocks:
items:
- description: USB2 PHY clock.
- description: USB2 PHY APB clock.
- description: USB3.2/DisplayPort combo PHY clock.
- description: USB3.2/DisplayPort combo PHY firmware clock.
clock-names:
items:
- const: usb2
- const: usb2_apb
- const: usb3
- const: usb3_fw
resets:
items:
- description: USB2 PHY reset.
- description: USB2 PHY APB reset.
- description: USB3.2/DisplayPort combo PHY reset.
reset-names:
items:
- const: usb2
- const: usb2_apb
- const: usb3
power-domains:
maxItems: 1
orientation-switch:
type: boolean
description:
Indicates the PHY as a handler of USB Type-C orientation changes
google,usb-cfg-csr:
description:
A phandle to a syscon node used to access the USB configuration
registers. These registers are the top-level wrapper of the USB
subsystem and provide control and status for the integrated USB
controller and USB PHY.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to the syscon node.
- description: USB2 PHY configuration register offset.
required:
- compatible
- reg
- reg-names
- "#phy-cells"
- clocks
- clock-names
- resets
- reset-names
- power-domains
- orientation-switch
- google,usb-cfg-csr
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
usb-phy@c410000 {
compatible = "google,lga-usb-phy";
reg = <0 0x0c410000 0 0x20000>,
<0 0x0c430000 0 0x1000>,
<0 0x0c440000 0 0x10000>,
<0 0x0c637000 0 0xa0>;
reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top";
#phy-cells = <1>;
clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>,
<&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>;
clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw";
resets = <&hsion_resets_usb2_phy>,
<&hsion_resets_u2phy_apb>,
<&hsion_resets_usb3_phy>;
reset-names = "usb2", "usb2_apb", "usb3";
power-domains = <&hsio_n_usb_pd>;
orientation-switch;
google,usb-cfg-csr = <&usb_cfg_csr 0x14>;
};
};
...
|
