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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MFlexGraphics Power and Frequency Controller
maintainers:
- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
description:
A special-purpose embedded MCU to control power and frequency of GPU devices
using MediaTek Flexible Graphics integration hardware.
properties:
$nodename:
pattern: '^power-controller@[a-f0-9]+$'
compatible:
enum:
- mediatek,mt8196-gpufreq
reg:
items:
- description: GPR memory area
- description: RPC memory area
- description: SoC variant ID register
reg-names:
items:
- const: gpr
- const: rpc
- const: hw-revision
clocks:
items:
- description: main clock of the embedded controller (EB)
- description: core PLL
- description: stack 0 PLL
- description: stack 1 PLL
clock-names:
items:
- const: eb
- const: core
- const: stack0
- const: stack1
mboxes:
items:
- description: FastDVFS events
- description: frequency control
- description: sleep control
- description: timer control
- description: frequency hopping control
- description: hardware voter control
- description: FastDVFS control
mbox-names:
items:
- const: fast-dvfs-event
- const: gpufreq
- const: sleep
- const: timer
- const: fhctl
- const: ccf
- const: fast-dvfs
memory-region:
items:
- description: phandle to the GPUEB shared memory
"#clock-cells":
const: 1
"#power-domain-cells":
const: 0
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- mboxes
- mbox-names
- memory-region
- "#clock-cells"
- "#power-domain-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
power-controller@4b09fd00 {
compatible = "mediatek,mt8196-gpufreq";
reg = <0x4b09fd00 0x80>,
<0x4b800000 0x1000>,
<0x4b860128 0x4>;
reg-names = "gpr", "rpc", "hw-revision";
clocks = <&topckgen CLK_TOP_MFG_EB>,
<&mfgpll CLK_MFG_AO_MFGPLL>,
<&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
<&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
clock-names = "eb", "core", "stack0", "stack1";
mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
<&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
<&gpueb_mbox 7>;
mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
"ccf", "fast-dvfs";
memory-region = <&gpueb_shared_memory>;
#clock-cells = <1>;
#power-domain-cells = <0>;
};
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