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/*
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <mach/iomux-mx6q.h>
/* Common pads for PhyCard board */
static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
/* User LEDs */
MX6Q_PAD_GPIO_7__GPIO_1_7, // Led Green
MX6Q_PAD_EIM_D20__GPIO_3_20, // Led Red
MX6Q_PAD_EIM_CS1__GPIO_2_24, // User Led -> HW Changed to Second TS Interrupt
MX6Q_PAD_EIM_D25__UART3_RXD,
MX6Q_PAD_EIM_D24__UART3_TXD,
MX6Q_PAD_EIM_D30__UART3_CTS,
MX6Q_PAD_EIM_D31__UART3_RTS,
/* ENET */
MX6Q_PAD_ENET_MDC__ENET_MDC, //ETH_MDC
MX6Q_PAD_ENET_MDIO__ENET_MDIO, //ETH_MDIO
MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN, //ETH_RXDV, CONFIG2
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK, //ETH_TXC
MX6Q_PAD_ENET_RX_ER__ENET_RX_ER, //ETH_RXER
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN, //ETH_TXEN
MX6Q_PAD_ENET_RXD0__ENET_RDATA_0, //ETH_RXD0
MX6Q_PAD_ENET_RXD1__ENET_RDATA_1, //ETH_RXD1, PHYAD2
MX6Q_PAD_ENET_TXD0__ENET_TDATA_0, //ETH_TXD0
MX6Q_PAD_ENET_TXD1__ENET_TDATA_1, //ETH_TXD1
MX6Q_PAD_KEY_COL0__ENET_RDATA_3, //ETH_RXD3, PHYAD0
MX6Q_PAD_KEY_ROW0__ENET_TDATA_3, //ETH_TXD3
MX6Q_PAD_KEY_ROW1__ENET_COL, //CONFIG0, ETH_COL
MX6Q_PAD_KEY_COL2__ENET_RDATA_2, //ETH_RXD2, PHYAD1
MX6Q_PAD_KEY_ROW2__ENET_TDATA_2, //ETH_TXD2
MX6Q_PAD_KEY_COL3__ENET_CRS, //CONFIG1
MX6Q_PAD_GPIO_18__ENET_RX_CLK, //ETH_RXC
MX6Q_PAD_GPIO_19__ENET_TX_ER, //ETH_INT
/* SD2 */
MX6Q_PAD_SD2_CLK__USDHC2_CLK,
MX6Q_PAD_SD2_CMD__USDHC2_CMD,
MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
/* SD2_CD and SD2_WP */
MX6Q_PAD_GPIO_2__GPIO_1_2,
MX6Q_PAD_GPIO_4__GPIO_1_4,
/* SD3 */
MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
MX6Q_PAD_SD3_RST__GPIO_7_8,
/* SD3_CD and SD3_WP */
MX6Q_PAD_CSI0_DAT4__GPIO_5_22,
MX6Q_PAD_CSI0_DAT5__GPIO_5_23,
/* SPI3 */
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK,
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI,
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO,
MX6Q_PAD_DISP0_DAT3__GPIO_4_24, /*SS0*/
MX6Q_PAD_DISP0_DAT4__GPIO_4_25, /*SS1*/
MX6Q_PAD_DISP0_DAT5__GPIO_4_26, /*SS2*/
MX6Q_PAD_DISP0_DAT6__GPIO_4_27, /*SS3*/
MX6Q_PAD_EIM_D29__GPIO_3_29,
MX6Q_PAD_DISP0_DAT20__GPIO_5_14, /* HDA select / interrupt AC97 */
MX6Q_PAD_GPIO_6__GPIO_1_6,
MX6Q_PAD_GPIO_9__GPIO_1_9,
/* MCLK for csi0 */
MX6Q_PAD_GPIO_0__CCM_CLKO,
MX6Q_PAD_GPIO_3__CCM_CLKO2,
/* ESAI */
MX6Q_PAD_NANDF_CS2__ESAI1_TX0,
MX6Q_PAD_NANDF_CS3__ESAI1_TX1,
/* I2C1 */
MX6Q_PAD_EIM_D28__I2C1_SDA,
MX6Q_PAD_EIM_D21__I2C1_SCL,
/* I2C2 */
MX6Q_PAD_EIM_EB2__I2C2_SCL,
MX6Q_PAD_EIM_D16__I2C2_SDA,
/* DISPLAY */
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4,
/* LVDS0 BACKLIGHT ENABLE */
MX6Q_PAD_CSI0_DAT6__GPIO_5_24,
MX6Q_PAD_EIM_OE__GPIO_2_25,
/* TX phyCARD STMPE Int */
MX6Q_PAD_DISP0_DAT8__GPIO_4_29,
/* DISP0 DET */
//MX6Q_PAD_EIM_D31__GPIO_3_31,
/* DISP0 RESET */
MX6Q_PAD_EIM_WAIT__GPIO_5_0,
/* USBOTG ID pin */
MX6Q_PAD_GPIO_1__USBOTG_ID,
MX6Q_PAD_KEY_ROW4__GPIO_4_15, /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC,
MX6Q_PAD_GPIO_0__GPIO_1_0, /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC, /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
/* 1-Wire interface data pin */
MX6Q_PAD_CSI0_DAT8__GPIO_5_26,
/* AUDIO PADS */
MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC,
MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD,
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS,
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD,
// MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC,
MX6Q_PAD_GPIO_17__GPIO_7_12,
/* ipu2 csi1 */
MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK,
MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC,
MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC,
MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN,
MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0,
MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1,
MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2,
MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3,
MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4,
MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5,
MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6,
MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7,
MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8,
MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9,
MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10,
MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11,
MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12,
MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13,
MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14,
MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15,
MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16,
MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17,
MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18,
MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19,
};
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