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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for NXP LS1088A RDB Board.
*
* Copyright 2017 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};
&i2c0 {
status = "okay";
i2c-switch@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temp-sensor@4c {
compatible = "adi,adt7461a";
reg = <0x4c>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
/* IRQ10_B */
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
&ifc {
ranges = <0 0 0x5 0x30000000 0x00010000
2 0 0x5 0x20000000 0x00010000>;
status = "okay";
nand@0,0 {
compatible = "fsl,ifc-nand";
reg = <0x0 0x0 0x10000>;
};
fpga: board-control@2,0 {
compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
};
};
&qspi {
status = "okay";
s25fs512s0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <0>;
spi-rx-bus-width = <1>;
spi-tx-bus-width = <1>;
};
s25fs512s1: flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
reg = <1>;
spi-rx-bus-width = <1>;
spi-tx-bus-width = <1>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&esdhc {
status = "okay";
};
&sata {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
dr_mode = "otg";
status = "okay";
};
&emdio1 {
/* Freescale F104 PHY1 */
mdio1_phy1: emdio1_phy@1 {
reg = <0x1c>;
phy-connection-type = "qsgmii";
};
mdio1_phy2: emdio1_phy@2 {
reg = <0x1d>;
phy-connection-type = "qsgmii";
};
mdio1_phy3: emdio1_phy@3 {
reg = <0x1e>;
phy-connection-type = "qsgmii";
};
mdio1_phy4: emdio1_phy@4 {
reg = <0x1f>;
phy-connection-type = "qsgmii";
};
/* F104 PHY2 */
mdio1_phy5: emdio1_phy@5 {
reg = <0x0c>;
phy-connection-type = "qsgmii";
};
mdio1_phy6: emdio1_phy@6 {
reg = <0x0d>;
phy-connection-type = "qsgmii";
};
mdio1_phy7: emdio1_phy@7 {
reg = <0x0e>;
phy-connection-type = "qsgmii";
};
mdio1_phy8: emdio1_phy@8 {
reg = <0x0f>;
phy-connection-type = "qsgmii";
};
};
&emdio2 {
/* Aquantia AQR105 10G PHY */
mdio2_phy1: emdio2_phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
interrupts = <0 2 0x4>;
reg = <0x0>;
phy-connection-type = "xfi";
};
};
/* DPMAC connections to external PHYs
* based on LS1088A RM RevC - $24.1.2 SerDes Options
*/
/* DPMAC1 is 10G SFP+, fixed link */
&dpmac2 {
phy-handle = <&mdio2_phy1>;
};
&dpmac3 {
phy-handle = <&mdio1_phy5>;
};
&dpmac4 {
phy-handle = <&mdio1_phy6>;
};
&dpmac5 {
phy-handle = <&mdio1_phy7>;
};
&dpmac6 {
phy-handle = <&mdio1_phy8>;
};
&dpmac7 {
phy-handle = <&mdio1_phy1>;
};
&dpmac8 {
phy-handle = <&mdio1_phy2>;
};
&dpmac9 {
phy-handle = <&mdio1_phy3>;
};
&dpmac10 {
phy-handle = <&mdio1_phy4>;
};
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