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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
/dts-v1/;
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8dxl.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Freescale i.MX8DXL EVK";
compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl";
interrupt-parent = <&gic>;
#address-cells = <0x2>;
#size-cells = <0x2>;
aliases {
mmc0 = &usdhc1;
serial4 = &cm40_lpuart;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
enable-method = "psci";
reg = <0x0 0x1>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
scu {
compatible = "fsl,imx-scu";
mbox-names = "tx0", "tx1", "tx2", "tx3",
"rx0", "rx1", "rx2", "rx3",
"gip3";
mboxes = <&lsio_mu2 0 0
&lsio_mu2 0 1
&lsio_mu2 0 2
&lsio_mu2 0 3
&lsio_mu2 1 0
&lsio_mu2 1 1
&lsio_mu2 1 2
&lsio_mu2 1 3
&lsio_mu2 3 3>;
pd: imx8dxl-pd {
compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
clk: clock-controller {
compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
#clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
iomuxc: pinctrl {
compatible = "fsl,imx8dxl-iomuxc";
};
};
soc {
compatible = "fsl,imx8qxp-soc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
clock-frequency = <8333333>;
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
clk_dummy: clock-dummy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "clk_dummy";
};
xtal32k: clock-xtal32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xtal_32KHz";
};
xtal24m: clock-xtal24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "xtal_24MHz";
};
pci@bf700000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
<0 0 0 2 &gic GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
<0 0 0 3 &gic GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
<0 0 0 4 &gic GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xbf700000 0x0 0x00100000>;
ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
};
/* For early console */
serial@5a060000 {
compatible = "fsl,imx8dxl-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x0 0x5a060000 0x0 0x1000>;
};
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-cm40.dtsi"
};
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-adma.dtsi"
#include "imx8dxl-ss-conn.dtsi"
&edma0 {
status = "disabled";
};
&acm {
status = "disabled";
};
&iomuxc {
pinctrl_cm40_lpuart: cm40_lpuartgrp {
fsl,pins = <
IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&lsio_mu1 {
status = "disabled";
};
&lsio_mu2 {
status = "okay";
};
&lsio_gpio0 {
status = "disabled";
};
&lsio_gpio1 {
status = "disabled";
};
&lsio_gpio2 {
status = "disabled";
};
&lsio_gpio3 {
status = "disabled";
};
&lsio_gpio4 {
status = "disabled";
};
&lsio_gpio5 {
status = "disabled";
};
&lsio_gpio6 {
status = "disabled";
};
&lsio_gpio7 {
status = "disabled";
};
&cm40_intmux {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
&cm40_intmux {
status = "okay";
};
&cm40_lpuart {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cm40_lpuart>;
status = "okay";
};
/delete-node/ &lpuart0;
|
