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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-sr-som.dtsi"
#include "imx8mp-hummingboard-pulse-codec.dtsi"
#include "imx8mp-hummingboard-pulse-common.dtsi"
#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
#include "imx8mp-hummingboard-pulse-m2con.dtsi"
#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
/ {
model = "SolidRun i.MX8MP HummingBoard Pulse";
compatible = "solidrun,imx8mp-hummingboard-pulse",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
ethernet1 = &pcie_eth;
};
};
&fec {
/* this board does not use second phy / ethernet on SoM */
status = "disabled";
};
&gpio1 {
pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>;
pinctrl-names = "default";
m2-reset-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "m2-reset";
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
<&m2_wwan_wake_pins>;
pcie_eth_pins: pinctrl-pcie-eth-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0
>;
};
};
&pcie {
pinctrl-0 = <&pcie_eth_pins>;
pinctrl-names = "default";
reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
root@0,0 {
compatible = "pci16c3,abcd";
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
/* Intel i210 */
pcie_eth: ethernet@1,0 {
compatible = "pci8086,157b";
reg = <0x00010000 0 0 0 0>;
};
};
};
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};
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