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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright 2025 NXP
*/
#ifndef __IMX952_POWER_H__
#define __IMX952_POWER_H__
#define IMX952_PD_ANA 0
#define IMX952_PD_AON 1
#define IMX952_PD_BBSM 2
#define IMX952_PD_CAMERA 3
#define IMX952_PD_CCMSRCGPC 4
#define IMX952_PD_A55C0 5
#define IMX952_PD_A55C1 6
#define IMX952_PD_A55C2 7
#define IMX952_PD_A55C3 8
#define IMX952_PD_A55P 9
#define IMX952_PD_DDR 10
#define IMX952_PD_DISPLAY 11
#define IMX952_PD_GPU 12
#define IMX952_PD_HSIO_TOP 13
#define IMX952_PD_HSIO_WAON 14
#define IMX952_PD_M7 15
#define IMX952_PD_NETC 16
#define IMX952_PD_NOC 17
#define IMX952_PD_NPU 18
#define IMX952_PD_VPU 19
#define IMX952_PD_WAKEUP 20
#define IMX952_PERF_M33 0
#define IMX952_PERF_WAKEUP 1
#define IMX952_PERF_M7 2
#define IMX952_PERF_DRAM 3
#define IMX952_PERF_HSIO 4
#define IMX952_PERF_NPU 5
#define IMX952_PERF_NOC 6
#define IMX952_PERF_A55 7
#define IMX952_PERF_GPU 8
#define IMX952_PERF_VPU 9
#define IMX952_PERF_CAM 10
#define IMX952_PERF_DISP 11
#endif
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