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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a35";
reg = <0>;
device_type = "cpu";
enable-method = "psci";
};
};
arm-pmu {
compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
interrupt-parent = <&intc>;
};
arm_wdt: watchdog {
compatible = "arm,smc-wdt";
arm,smc-id = <0xbc000000>;
status = "disabled";
};
ck_flexgen_08: clock-64000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <64000000>;
};
ck_flexgen_51: clock-200000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
scmi: scmi {
compatible = "linaro,scmi-optee";
#address-cells = <1>;
#size-cells = <0>;
linaro,optee-channel-id = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
scmi_reset: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
arm,no-tick-in-suspend;
};
soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x0 0x80000000>;
dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>;
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <2>;
rifsc: bus@42080000 {
compatible = "st,stm32mp21-rifsc", "simple-bus";
reg = <0x42080000 0x0 0x1000>;
ranges;
dma-ranges;
#address-cells = <1>;
#size-cells = <2>;
#access-controller-cells = <1>;
usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x0 0x400>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_flexgen_08>;
access-controllers = <&rifsc 32>;
status = "disabled";
};
};
syscfg: syscon@44230000 {
compatible = "st,stm32mp21-syscfg", "syscon";
reg = <0x44230000 0x0 0x10000>;
};
intc: interrupt-controller@4ac10000 {
compatible = "arm,gic-400";
reg = <0x4ac10000 0x0 0x1000>,
<0x4ac20000 0x0 0x20000>,
<0x4ac40000 0x0 0x20000>,
<0x4ac60000 0x0 0x20000>;
#interrupt-cells = <3>;
interrupt-controller;
};
};
};
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