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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
/* SE_GCC clocks */
#define SE_GCC_EEE_EMAC0_CLK 0
#define SE_GCC_EEE_EMAC0_CLK_SRC 1
#define SE_GCC_EEE_EMAC1_CLK 2
#define SE_GCC_EEE_EMAC1_CLK_SRC 3
#define SE_GCC_EMAC0_AXI_CLK 4
#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5
#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6
#define SE_GCC_EMAC0_PHY_AUX_CLK 7
#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8
#define SE_GCC_EMAC0_PTP_CLK 9
#define SE_GCC_EMAC0_PTP_CLK_SRC 10
#define SE_GCC_EMAC0_RGMII_CLK 11
#define SE_GCC_EMAC0_RGMII_CLK_SRC 12
#define SE_GCC_EMAC0_RPCS_RX_CLK 13
#define SE_GCC_EMAC0_RPCS_TX_CLK 14
#define SE_GCC_EMAC0_XGXS_RX_CLK 15
#define SE_GCC_EMAC0_XGXS_TX_CLK 16
#define SE_GCC_EMAC1_AXI_CLK 17
#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18
#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19
#define SE_GCC_EMAC1_PHY_AUX_CLK 20
#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21
#define SE_GCC_EMAC1_PTP_CLK 22
#define SE_GCC_EMAC1_PTP_CLK_SRC 23
#define SE_GCC_EMAC1_RGMII_CLK 24
#define SE_GCC_EMAC1_RGMII_CLK_SRC 25
#define SE_GCC_EMAC1_RPCS_RX_CLK 26
#define SE_GCC_EMAC1_RPCS_TX_CLK 27
#define SE_GCC_EMAC1_XGXS_RX_CLK 28
#define SE_GCC_EMAC1_XGXS_TX_CLK 29
#define SE_GCC_FRQ_MEASURE_REF_CLK 30
#define SE_GCC_GP1_CLK 31
#define SE_GCC_GP1_CLK_SRC 32
#define SE_GCC_GP2_CLK 33
#define SE_GCC_GP2_CLK_SRC 34
#define SE_GCC_GPLL0 35
#define SE_GCC_GPLL0_OUT_EVEN 36
#define SE_GCC_GPLL2 37
#define SE_GCC_GPLL4 38
#define SE_GCC_GPLL5 39
#define SE_GCC_MMU_2_TCU_VOTE_CLK 40
#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41
#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42
#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43
#define SE_GCC_QUPV3_WRAP0_S0_CLK 44
#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45
#define SE_GCC_QUPV3_WRAP0_S1_CLK 46
#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47
#define SE_GCC_QUPV3_WRAP0_S2_CLK 48
#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49
#define SE_GCC_QUPV3_WRAP0_S3_CLK 50
#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51
#define SE_GCC_QUPV3_WRAP0_S4_CLK 52
#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53
#define SE_GCC_QUPV3_WRAP0_S5_CLK 54
#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55
#define SE_GCC_QUPV3_WRAP0_S6_CLK 56
#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57
#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58
#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59
#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60
#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61
#define SE_GCC_QUPV3_WRAP1_S0_CLK 62
#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63
#define SE_GCC_QUPV3_WRAP1_S1_CLK 64
#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65
#define SE_GCC_QUPV3_WRAP1_S2_CLK 66
#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67
#define SE_GCC_QUPV3_WRAP1_S3_CLK 68
#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69
#define SE_GCC_QUPV3_WRAP1_S4_CLK 70
#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71
#define SE_GCC_QUPV3_WRAP1_S5_CLK 72
#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73
#define SE_GCC_QUPV3_WRAP1_S6_CLK 74
#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75
#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76
/* SE_GCC power domains */
#define SE_GCC_EMAC0_GDSC 0
#define SE_GCC_EMAC1_GDSC 1
/* SE_GCC resets */
#define SE_GCC_EMAC0_BCR 0
#define SE_GCC_EMAC1_BCR 1
#define SE_GCC_QUPV3_WRAPPER_0_BCR 2
#define SE_GCC_QUPV3_WRAPPER_1_BCR 3
#endif
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