blob: 42d981982b645c8711d3a67b2533674846cc8dcd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
/* include/linux/tegra_uart.h
*
* Copyright (C) 2011 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef _TEGRA_UART_H_
#define _TEGRA_UART_H_
#include <linux/clk.h>
struct uart_clk_parent {
const char *name;
struct clk *parent_clk;
unsigned long fixed_clk_rate;
};
/*
* struct tegra_uart_platform_data - Platform data for tegra high speed uart.
*
* @parent_clk_list: The parent clock source list. The best clock source will be
* selected such that the error between desired baudrate and
* calculated baudrate within 2% error. The searching will
* start from index 0 and so the preference of clock source
* selection will be high on index 0 and it will go lower
* with increasing index.
* @parent_clk_count: The number of clock source list.
*/
struct tegra_uart_platform_data {
void (*wake_peer)(struct uart_port *);
struct uart_clk_parent *parent_clk_list;
int parent_clk_count;
};
int tegra_uart_is_tx_empty(struct uart_port *);
void tegra_uart_request_clock_on(struct uart_port *);
void tegra_uart_set_mctrl(struct uart_port *, unsigned int);
void tegra_uart_request_clock_off(struct uart_port *uport);
#endif /* _TEGRA_UART_H_ */
|