clk: thead: th1520-ap: Correctly handle flags for dividers

Unlike the gate clocks which make no use of flags, most dividers in
TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED
flag. We couldn't simply ignore the flag, which causes wrong results
when calculating the clock rates.

Add a member to ccu_div_internal for defining the flags, and pass it to
divider_recalc_rate(). With this fix, frequency of all the clocks match
the Linux kernel's calculation.

Fixes: e6bfa6fc94f ("clk: thead: Port clock controller driver of TH1520 SoC")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
index b80ad05b8ad..822cf0809d5 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -32,6 +32,7 @@ struct ccu_internal {
 struct ccu_div_internal {
 	u8 shift;
 	u8 width;
+	unsigned long flags;
 };
 
 struct ccu_common {
@@ -79,6 +80,7 @@ struct ccu_pll {
 	{								\
 		.shift	= _shift,					\
 		.width	= _width,					\
+		.flags	= _flags,					\
 	}
 
 #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags)	\
@@ -182,7 +184,7 @@ static unsigned long ccu_div_get_rate(struct clk *clk)
 	val = val >> cd->div.shift;
 	val &= GENMASK(cd->div.width - 1, 0);
 	rate = divider_recalc_rate(clk, clk_get_parent_rate(clk), val, NULL,
-				   0, cd->div.width);
+				   cd->div.flags, cd->div.width);
 
 	return rate;
 }