diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2024-11-27 13:35:10 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-02-26 13:06:02 +0200 |
| commit | 026a1ab2fa6eb0101538cc5186ee20ff01b220fa (patch) | |
| tree | 3850fb47df5fd8dc785a4384b474e8f57cb63cb4 | |
| parent | 5643a85205643ea95078119d1406eaa436a4aca5 (diff) | |
video: tegra20: dc: remove hardcoded Tegra 2 specific parts
Since pinmux driver now is available for Tegra 2, these parts may
be removed from here and defined either in device tree or in
the device board files.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 | ||||
| -rw-r--r-- | drivers/video/tegra20/tegra-dc.c | 18 |
2 files changed, 4 insertions, 16 deletions
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h index 861b3d5d07c..82685353bd1 100644 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -32,6 +32,7 @@ enum clock_id { CLOCK_ID_COUNT, /* number of clocks */ CLOCK_ID_NONE = -1, + CLOCK_ID_DISPLAY2 = CLOCK_ID_NONE, /* for compatibility */ }; /* The clocks supported by the hardware */ @@ -159,6 +160,7 @@ enum periph_id { PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, + PERIPH_ID_DSIB = CLOCK_ID_NONE, /* for compatibility */ }; enum pll_out_id { diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index bd0d8ca7b8f..d54279ebda1 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -311,15 +311,10 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv, * We halve the rate if DISP1 parent is PLLD, since actual parent * is plld_out0 which is PLLD divided by 2. */ - if (priv->clk_parent->id == CLOCK_ID_DISPLAY) + if (priv->clk_parent->id == CLOCK_ID_DISPLAY || + priv->clk_parent->id == CLOCK_ID_DISPLAY2) rate /= 2; -#ifndef CONFIG_TEGRA20 - /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */ - if (priv->clk_parent->id == CLOCK_ID_DISPLAY2) - rate /= 2; -#endif - /* * The pixel clock divider is in 7.1 format (where the bottom bit * represents 0.5). Here we calculate the divider needed to get from @@ -366,10 +361,6 @@ static int tegra_lcd_probe(struct udevice *dev) int ret; /* Initialize the Tegra display controller */ -#ifdef CONFIG_TEGRA20 - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); -#endif - if (priv->soc->has_pgate) { uint powergate; @@ -409,11 +400,6 @@ static int tegra_lcd_probe(struct udevice *dev) return -1; } -#ifdef CONFIG_TEGRA20 - pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); - pinmux_tristate_disable(PMUX_PINGRP_GPU); -#endif - ret = panel_enable_backlight(priv->panel); if (ret) { debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret); |