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authorJudith Mendez <jm@ti.com>2025-04-17 18:43:32 -0500
committerTom Rini <trini@konsulko.com>2025-04-24 10:44:52 -0600
commit02c6913a97934c3b68629739b9c6273539e37a96 (patch)
treea0154e6f281697cd01b3e25944c40ffa38212a06
parentc511c708aaf00d850f2c8eee7d083466a04109b7 (diff)
mmc: am654_sdhci: Fix HIGH_SPEED_ENA
High Speed enable bit switches data launch from the falling clock edge (half cycle timing) to the rising clock edge (full cycle timing). For all SD UHS modes, data launch must happen at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and SDR25 modes. For all HS modes, data launch must happen at the falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
-rw-r--r--drivers/mmc/am654_sdhci.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index e4fa8a88565..28d82afd012 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -412,8 +412,7 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
*/
case SD_HS:
case MMC_HS:
- case UHS_SDR12:
- case UHS_SDR25:
+ case MMC_HS_52:
val &= ~SDHCI_CTRL_HISPD;
default:
break;