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authorMinda Chen <minda.chen@starfivetech.com>2025-03-06 14:20:30 +0800
committerMarek Vasut <marex@denx.de>2025-03-17 01:55:19 +0100
commit05aa34cef90caf9c8bbf73abb32a79392996785f (patch)
tree622b184609f9d5e4dde22c63829a45a9f689f6ab
parentd0f8a9511e67e96f80fe624d304dd71f4a023e04 (diff)
spl: starfive: visionfive2: Disable USB overcurrent pin by default.
For some JH7110 boards, USB host overcurent pin is not reserved, To make USB host work, overcurrent pin must be disabled. So set the pin default disabled in spl stage. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Tested-by: E Shattow <lucent@gmail.com>
-rw-r--r--arch/riscv/include/asm/arch-jh7110/gpio.h5
-rw-r--r--board/starfive/visionfive2/spl.c3
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
index 90aa2f8a9ed..be2a1e0d1c8 100644
--- a/arch/riscv/include/asm/arch-jh7110/gpio.h
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -63,6 +63,11 @@ enum gpio_state {
GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+#define SYS_IOMUX_DIN_DISABLED(gpi)\
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+ ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
#define SYS_IOMUX_SET_DS(gpio, ds) \
clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 22afd76c6b9..1538d6aec73 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -103,6 +103,9 @@ void board_init_f(ulong dummy)
JH7110_CLK_CPU_ROOT_MASK,
BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+ /* Set USB overcurrent overflow pin disable */
+ SYS_IOMUX_DIN_DISABLED(2);
+
ret = spl_board_init_f();
if (ret) {
debug("spl_board_init_f init failed: %d\n", ret);