apalis-imx6: add usage of KSZ9XX12016.11-toradex-next2016.11-toradex

Backport usage of a new KSZ9XX1 PHY by Apalis iMX6, the old driver
located in micrel.c still used by other boards. If a board
wants to use a new PHY the old one must be disabled.

Backported from:
commit f72e48ba4d98 ("board: apalis_imx6: Add KSZ9131 phy skew settings")
Related-to: ELB-4181
Signed-off-by: Oleksii Bidnichenko <oleksii.bidnichenko@toradex.com>

8 files changed, 96 insertions, 20 deletions

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index b2bb8757897..f5f51fcda83 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -208,22 +208,79 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
-	/* control data pad skew - devaddr = 0x02, register = 0x04 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+	int tmp;
+
+	switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
+	case PHY_ID_KSZ9131:
+		/* read rxc dll control - devaddr = 0x02, register = 0x4c */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on RXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   tmp);
+		/* read txc dll control - devaddr = 0x02, register = 0x4d */
+		tmp = ksz9031_phy_extended_read(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC);
+		/* disable rxdll bypass (enable 2ns skew delay on TXC) */
+		tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
+		/* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   tmp);
+
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x007d);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x7777);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0xdddd);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0007);
+		break;
+	case PHY_ID_KSZ9031:
+	default:
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03FF);
+		break;
+	}
+
 	return 0;
 }
 
@@ -480,8 +537,6 @@ int board_mmc_init(bd_t *bis)
 
 int board_phy_config(struct phy_device *phydev)
 {
-	ksz9031_center_flp_timing(phydev);
-
 	mx6_rgmii_rework(phydev);
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index bfd8cc01383..138c2ec575d 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -55,3 +55,5 @@ CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_PHY_MICREL=n
+CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
index 0dcb6fcf74b..7e87f38f665 100644
--- a/configs/apalis_imx6_nospl_com_defconfig
+++ b/configs/apalis_imx6_nospl_com_defconfig
@@ -42,3 +42,5 @@ CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_PHY_MICREL=n
+CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
index 3846f37152d..cfd22c6cdde 100644
--- a/configs/apalis_imx6_nospl_it_defconfig
+++ b/configs/apalis_imx6_nospl_it_defconfig
@@ -42,3 +42,5 @@ CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_PHY_MICREL=n
+CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/apalis_imx6_tezi_defconfig b/configs/apalis_imx6_tezi_defconfig
index 80e8e1e1c11..ef0f02226d7 100644
--- a/configs/apalis_imx6_tezi_defconfig
+++ b/configs/apalis_imx6_tezi_defconfig
@@ -54,3 +54,5 @@ CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_PHY_MICREL=n
+CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 4b2e519ab9f..0058b6ad350 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -103,8 +103,7 @@
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		6
 #define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9031
+#define CONFIG_PHY_MICREL_KSZ90X1
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		4096
 #define CONFIG_TFTP_TSIZE
diff --git a/include/micrel.h b/include/micrel.h
index 783dc634e2c..a03b8dd7b97 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -23,6 +23,16 @@
 #define MII_KSZ9031_FLP_BURST_TX_LO		0x3
 #define MII_KSZ9031_FLP_BURST_TX_HI		0x4
 
+#define MII_KSZ9x31_SILICON_REV_MASK		0xfffff0
+
+#define MII_KSZ9131_RXTXDLL_BYPASS		BIT(12)
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL	0x4c
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL	0x4d
+
+#define PHY_ID_KSZ9031				0x00221620
+#define PHY_ID_KSZ9131				0x00221640
+
+
 /* Registers */
 #define MMD_ACCESS_CONTROL	0xd
 #define MMD_ACCESS_REG_DATA	0xe
@@ -35,6 +45,9 @@ int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
 			       int regnum, u16 mode, u16 val);
 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
 			      int regnum, u16 mode);
+int ksz9xx1_phy_get_id(struct phy_device *phydev);
+#ifndef CONFIG_PHY_MICREL_KSZ90X1
 int ksz9031_center_flp_timing(struct phy_device *phydev);
+#endif
 
 #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 724fcfc4264..63fd60a76ac 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3556,6 +3556,7 @@ CONFIG_PHY_MAX_ADDR
 CONFIG_PHY_MICREL
 CONFIG_PHY_MICREL_KSZ9021
 CONFIG_PHY_MICREL_KSZ9031
+CONFIG_PHY_MICREL_KSZ90X1
 CONFIG_PHY_MODE_NEED_CHANGE
 CONFIG_PHY_NATSEMI
 CONFIG_PHY_REALTEK