diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-02-18 16:35:02 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:54:00 -0600 |
| commit | 19f20cfc49e385dd5ae5583ae68bd31f20de622c (patch) | |
| tree | a6150c8e9f1888d3b303eb69b113451e9d737045 | |
| parent | 8c172a423cb6268eb787142b748b50473b80d88c (diff) | |
configs: agilex5: Add configuration for malloc pool
Adding configuration for SPL malloc pool.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
| -rw-r--r-- | configs/socfpga_agilex5_defconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 60e625ea805..2a2c76113cd 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -30,6 +30,10 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_CACHE=y |