diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2021-06-30 16:50:09 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-07-10 18:12:42 +0200 |
| commit | 1cb87b929e1ec92dd1f984f265b29f500019b300 (patch) | |
| tree | ff70e5d18d9b997fcfa62a6ccc35cf1d395c997e | |
| parent | 668e205098215acf13f72b892aea9267dc23dd19 (diff) | |
arm: dts: imx8mm-venice-gw7901.dts: fix dsa switch configuration
Fix the dsa switch config:
- remove the unnecessary phy-mode from the switch itself
- added the necessary fixed-link node to the non-cpu ports required
for U-Boot DSA
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| -rw-r--r-- | arch/arm/dts/imx8mm-venice-gw7901.dts | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index 0216facb2ae..124e1e4e704 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -577,7 +577,6 @@ pinctrl-0 = <&pinctrl_ksz>; interrupt-parent = <&gpio4>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - phy-mode = "rgmii-id"; ports { #address-cells = <1>; @@ -587,24 +586,32 @@ reg = <0>; label = "lan1"; local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy0>; + phy-mode = "internal"; }; lan2: port@1 { reg = <1>; label = "lan2"; local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy1>; + phy-mode = "internal"; }; lan3: port@2 { reg = <2>; label = "lan3"; local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy2>; + phy-mode = "internal"; }; lan4: port@3 { reg = <3>; label = "lan4"; local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy3>; + phy-mode = "internal"; }; port@5 { @@ -619,6 +626,34 @@ }; }; }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + }; }; crypto@60 { |