diff options
| author | Michael Walle <mwalle@kernel.org> | 2026-03-18 15:29:17 +0100 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2026-03-23 14:27:24 +0800 |
| commit | 1f305f99d2001e96daa7e93da4da2bf56da9278e (patch) | |
| tree | aaac3707938564271582b2ea566e66ed99069ad9 | |
| parent | a5e46ecc3593960c2fe763a598a6fd804912f05b (diff) | |
armv7: ls102xa: fix SPI flash clock
Commit bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
broke the SPI boot on the LS1021ATSN board (ls1021atsn_qspi_defconfig)
at least.
The commit message reads
Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5
which means ClusterPLL/16
The original submitted patch had the following description:
Value 0xC is reserved. Replace it with correct value 0x5 which
is ClusterPLL/16
Unfortunatly, the little information which was there, was stripped even
further. Why is 0x5 the "correct" value? In fact, it seems that the
upper bit is just ignored and thus the value 0xC translates to 0x4 which
is ClusterPLL/20. This, will result in a SPI clock of 60MHz (if the PLL
is clocked at 1.2GHz). But even that is too much for the (default) 03h
read opcode (max 50MHz). Set the value to ClusterPLL/24 which is 50MHz.
Link: https://lore.kernel.org/r/1568804284-25162-1-git-send-email-kuldeep.singh@nxp.com/
Fixes: bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index a0c3da7f46d..51ba8733768 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -137,7 +137,7 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 -#define SCFG_QSPI_CLKSEL 0x50100000 +#define SCFG_QSPI_CLKSEL 0x30100000 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 |