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authorSimon Glass <sjg@chromium.org>2019-12-06 21:42:14 -0700
committerBin Meng <bmeng.cn@gmail.com>2019-12-15 11:44:16 +0800
commit26047f602983dadf833546f8d40b24c7b9beaca3 (patch)
tree39f878b7614162442ed36e7d71f8a37e146ca87d
parent69b1e9f4f83ec30d6e010312e932928132a2324e (diff)
x86: Allow removal of standard PCH drivers
These drivers are not needed on all platforms. While they are small, it is useful in TPL to drop then. Add Kconfig control to allow this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-rw-r--r--drivers/pch/Kconfig18
-rw-r--r--drivers/pch/Makefile4
2 files changed, 20 insertions, 2 deletions
diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig
index 18f006de24c..c49a92885aa 100644
--- a/drivers/pch/Kconfig
+++ b/drivers/pch/Kconfig
@@ -7,3 +7,21 @@ config PCH
northbridge / southbridge architecture that was previously used. The
PCH allows for higher performance since the memory functions are
handled in the CPU.
+
+config X86_PCH7
+ bool "Add support for Intel PCH7"
+ default y if X86
+ help
+ Enable this if your SoC uses Platform Controller Hub 7 (PCH7). This
+ dates from about 2011 and is used on baytrail, for example. The
+ PCH provides access to the GPIO and SPI base addresses, among other
+ functions.
+
+config X86_PCH9
+ bool "Add support for Intel PCH9"
+ default y if X86
+ help
+ Enable this if your SoC uses Platform Controller Hub 9 (PCH9). This
+ dates from about 2015 and is used on baytrail, for example. The
+ PCH provides access to the GPIO and SPI base addresses, among other
+ functions.
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
index 8ea6b7852ac..d5de3e48be1 100644
--- a/drivers/pch/Makefile
+++ b/drivers/pch/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += pch-uclass.o
-obj-y += pch7.o
-obj-y += pch9.o
+obj-$(CONFIG_X86_PCH7) += pch7.o
+obj-$(CONFIG_X86_PCH9) += pch9.o
obj-$(CONFIG_SANDBOX) += sandbox_pch.o