diff options
| author | Jonas Karlman <jonas@kwiboo.se> | 2025-07-30 23:52:46 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2025-08-30 23:26:08 +0800 |
| commit | 281c66f39b0e6b3b520976ad0535939141f148b8 (patch) | |
| tree | 734c4c466835d5e53c3e351c2396752814f7612c | |
| parent | 58d39bbd773965404cd8cc41ebb94488b48ac1a4 (diff) | |
rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support
Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3528.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index 06f20895acc..d58557ff56d 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) /* Might occur in cru assigned-clocks, can be ignored here */ case ACLK_BUS_VOPGL_ROOT: case BCLK_EMMC: + case CLK_REF_PCIE_INNER_PHY: case XIN_OSC0_DIV: ret = 0; break; |