diff options
| author | Jonas Karlman <jonas@kwiboo.se> | 2025-08-01 20:43:37 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2025-08-30 23:01:44 +0800 |
| commit | 2a6039a20994c192edb6786fa97714180bd663cf (patch) | |
| tree | 639ea37509f5b1104c595b0786842019ee6b544b | |
| parent | 0d966d3932e2e5e7d14301da9ced0d7a62fce367 (diff) | |
rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support
Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3576.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index e84a0943a94..125b08ee832 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case CLK_CPLL_DIV10: case FCLK_DDR_CM0_CORE: case ACLK_PHP_ROOT: + case CLK_REF_PCIE0_PHY: + case CLK_REF_PCIE1_PHY: ret = 0; break; #ifndef CONFIG_SPL_BUILD |