diff options
| author | Tom Rini <trini@konsulko.com> | 2025-01-12 19:28:54 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-01-12 19:28:54 -0600 |
| commit | 35d9b1d254773083ccf4dd12680663eb5433d910 (patch) | |
| tree | 583fce949bad04c4588ba0d6fe40aafe1ff144ec | |
| parent | bc157bb6667ed97e33be8ce8436c28baa275b295 (diff) | |
| parent | 46a7999160da3167497e08a444417aea26171197 (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
| -rw-r--r-- | arch/arm/include/asm/armv8/cpu.h | 32 | ||||
| -rw-r--r-- | board/hoperun/hihope-rzg2/hihope-rzg2.c | 8 | ||||
| -rw-r--r-- | board/renesas/rcar-common/gen3-common.c | 10 |
3 files changed, 26 insertions, 24 deletions
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..4dbb589aab8 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,13 @@ * Copyright 2018 NXP */ -#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A57 0xD07 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_CORTEX_A76 0xD0B +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) static inline unsigned int read_midr(void) { @@ -18,9 +20,17 @@ static inline unsigned int read_midr(void) return val; } -#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) -#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) -#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) +#define is_cortex_a(__n) \ + static inline int is_cortex_a##__n(void) \ + { \ + unsigned int midr = read_midr(); \ + midr &= MIDR_PARTNUM_MASK; \ + midr >>= MIDR_PARTNUM_SHIFT; \ + return midr == MIDR_PARTNUM_CORTEX_A##__n; \ + } + +is_cortex_a(35) +is_cortex_a(53) +is_cortex_a(57) +is_cortex_a(72) +is_cortex_a(76) diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 8b635ef71ac..d2c5aaacf66 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -6,6 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ +#include <asm/armv8/cpu.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/processor.h> @@ -66,12 +67,7 @@ int board_init(void) void reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); else writel(RST_CA57_CODE, RST_CA57RESCNT); diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/rcar-common/gen3-common.c index 4291e1d5bcb..004feca6180 100644 --- a/board/renesas/rcar-common/gen3-common.c +++ b/board/renesas/rcar-common/gen3-common.c @@ -7,6 +7,7 @@ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ +#include <asm/armv8/cpu.h> #include <dm.h> #include <fdt_support.h> #include <hang.h> @@ -50,14 +51,9 @@ int fdtdec_board_setup(const void *fdt_blob) void __weak reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) + else if (is_cortex_a57()) writel(RST_CA57_CODE, RST_CA57RESCNT); else hang(); |