diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-08-03 18:24:43 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-08-08 22:20:49 +0800 |
| commit | 3a1cd4ffd7483465bf24539e9ba94f92dd17cd5d (patch) | |
| tree | 1f41da754db58f107c7ea616df17f54e52f27a92 | |
| parent | 9a7881abeb8c57e6d132c9303e487409a5340e51 (diff) | |
arm: socfpga: misc: Exclude Agilex from clock manager base address retrieval
Agilex retrieves its clock manager address via probing its own clock
driver model during the SPL initialization.
Therefore, excluding Agilex from calling its clock driver in misc
driver to retrieve the clock manager address.
Once all SoC64 devices has been successfully transition to clock
driver model method, this implementation will be cleaned up.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 3089f823b20..eb0eeb7bef4 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -261,13 +261,11 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); - else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); |