diff options
| author | Jernej Skrabec <jernej.skrabec@gmail.com> | 2022-01-30 15:27:14 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-04-04 23:24:17 +0100 |
| commit | 40a9c200aff1b855f66745a1b9961668739ef6fb (patch) | |
| tree | d2755b61356c6dd370acab94fdc6ce1f7db7650f | |
| parent | 1772771ac00150c474a0936f675dc553f44be549 (diff) | |
sunxi: clock: H6/H616: Add resistor calibration
BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun50i_h6.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index e5846e6381f..32119ad1655 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -12,9 +12,14 @@ void clock_init_safe(void) struct sunxi_prcm_reg *const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - /* this seems to enable PLLs on H616 */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + /* this seems to enable PLLs on H616 */ setbits_le32(&prcm->sys_pwroff_gating, 0x10); + setbits_le32(&prcm->res_cal_ctrl, 2); + } + + clrbits_le32(&prcm->res_cal_ctrl, 1); + setbits_le32(&prcm->res_cal_ctrl, 1); clock_set_pll1(408000000); |