diff options
| author | Chris Morgan <macromorgan@hotmail.com> | 2024-09-19 09:00:22 -0500 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2024-10-25 20:48:41 +0800 |
| commit | 55f6d0535065ea968c1cceb6315055fc7c000046 (patch) | |
| tree | 64a481e905efc87c24ec3800e05c4439e26f9abd | |
| parent | 9119efab3f7fde899e8332e6a4a8cc99c482d325 (diff) | |
board: rockchip: Enable PD_VO before driver access
Enable the PD_VO power domain before driver access on the rk3568 SoC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | arch/arm/mach-rockchip/rk3568/rk3568.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 768a3739329..c9a32287e92 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -26,6 +26,8 @@ #define PMU_BASE_ADDR 0xfdd90000 #define PMU_NOC_AUTO_CON0 (0x70) #define PMU_NOC_AUTO_CON1 (0x74) +#define PMU_PWR_GATE_SFTCON (0xa0) +#define PMU_PD_VO_DWN_ENA BIT(7) #define EDP_PHY_GRF_BASE 0xfdcb0000 #define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) #define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) @@ -130,6 +132,10 @@ int arch_cpu_init(void) writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); + + /* Enable VO power domain for display */ + writel((PMU_PD_VO_DWN_ENA << 16), + PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); #endif return 0; } |