diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:56 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | 566ce04de4a2b4c66be8e13751dbb0bfe80117b3 (patch) | |
| tree | 0b9a0f18e8e3a3c97c9adc376056315553343d69 | |
| parent | 7953354b07bba8fa9599bf5d212308e6cdf9cbe2 (diff) | |
MIPS: Malta: Enable CM & L2 support
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| -rw-r--r-- | arch/mips/Kconfig | 2 | ||||
| -rw-r--r-- | board/imgtec/malta/lowlevel_init.S | 6 |
2 files changed, 2 insertions, 6 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 76714379a4c..f113b91de70 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -26,6 +26,8 @@ config TARGET_MALTA select DM select DM_SERIAL select DYNAMIC_IO_PORT_BASE + select MIPS_CM + select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS select SUPPORTS_BIG_ENDIAN diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index 3d48cdc1f47..6df4d9f719b 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -28,12 +28,6 @@ .globl lowlevel_init lowlevel_init: - /* disable any L2 cache for now */ - sync - mfc0 t0, CP0_CONFIG, 2 - ori t0, t0, 0x1 << 12 - mtc0 t0, CP0_CONFIG, 2 - /* detect the core card */ PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) lw t0, 0(t0) |