Merge tag 'u-boot-imx-master-20241013' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22644

- Add fast authentication method for i.MX8M signing.
- Migrate imx8mp-debix-model-a to OF_UPSTREAM.
- Update MAINTAINERS file globs for i.MX6/i.MX8MP DHSOM.
- Improve ELE driver.
- Add i.MX8MP Dummy clk to fix regression.

15 files changed, 267 insertions, 600 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 65176c8fb83..73efdcf9756 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -967,7 +967,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
 	imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
 	imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
-	imx8mp-debix-model-a.dtb \
 	imx8mp-dhcom-drc02.dtb \
 	imx8mp-dhcom-pdk2.dtb \
 	imx8mp-dhcom-pdk3.dtb \
diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
index 33bd89a8434..d5bd9f591e5 100644
--- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
@@ -20,6 +20,14 @@
 	};
 };
 
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+	bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+	bootph-pre-ram;
+};
+
 &crypto {
 	bootph-pre-ram;
 };
@@ -88,14 +96,6 @@
 	bootph-pre-ram;
 };
 
-&pmic {
-	bootph-pre-ram;
-
-	regulators {
-		bootph-pre-ram;
-	};
-};
-
 &reg_usdhc2_vmmc {
 	u-boot,off-on-delay-us = <20000>;
 };
diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts
deleted file mode 100644
index 58dae612b4b..00000000000
--- a/arch/arm/dts/imx8mp-debix-model-a.dts
+++ /dev/null
@@ -1,507 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- * Copyright 2022 Ideas on Board Oy
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/usb/pd.h>
-
-#include "imx8mp.dtsi"
-
-/ {
-	model = "Polyhex Debix Model A i.MX8MPlus board";
-	compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
-
-	chosen {
-		stdout-path = &uart2;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_led>;
-
-		led-0 {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-	};
-
-	reg_usdhc2_vmmc: regulator-usdhc2 {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-		regulator-name = "VSD_3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-};
-
-&A53_0 {
-	cpu-supply = <&buck2>;
-};
-
-&A53_1 {
-	cpu-supply = <&buck2>;
-};
-
-&A53_2 {
-	cpu-supply = <&buck2>;
-};
-
-&A53_3 {
-	cpu-supply = <&buck2>;
-};
-
-&eqos {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_eqos>;
-	phy-connection-type = "rgmii-id";
-	phy-handle = <&ethphy0>;
-	status = "okay";
-
-	mdio {
-		compatible = "snps,dwmac-mdio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@0 { /* RTL8211E */
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <20>;
-			reset-deassert-us = <200000>;
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	pmic: pmic@25 {
-		compatible = "nxp,pca9450c";
-		reg = <0x25>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-
-		regulators {
-			buck1: BUCK1 {
-				regulator-name = "BUCK1";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <2187500>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <3125>;
-			};
-
-			buck2: BUCK2 {
-				regulator-name = "BUCK2";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <2187500>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <3125>;
-				nxp,dvs-run-voltage = <950000>;
-				nxp,dvs-standby-voltage = <850000>;
-			};
-
-			buck4: BUCK4{
-				regulator-name = "BUCK4";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <3400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck5: BUCK5{
-				regulator-name = "BUCK5";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <3400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck6: BUCK6 {
-				regulator-name = "BUCK6";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <3400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo1: LDO1 {
-				regulator-name = "LDO1";
-				regulator-min-microvolt = <1600000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo2: LDO2 {
-				regulator-name = "LDO2";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1150000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo3: LDO3 {
-				regulator-name = "LDO3";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo4: LDO4 {
-				regulator-name = "LDO4";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo5: LDO5 {
-				regulator-name = "LDO5";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	status = "okay";
-};
-
-&i2c3 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	status = "okay";
-};
-
-&i2c4 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c4>;
-	status = "okay";
-
-	eeprom@50 {
-		compatible = "atmel,24c02";
-		reg = <0x50>;
-		pagesize = <16>;
-	};
-
-	rtc@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
-		#clock-cells = <0>;
-		clock-frequency = <32768>;
-		clock-output-names = "xin32k";
-		interrupt-parent = <&gpio2>;
-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_rtc_int>;
-	};
-};
-
-&i2c6 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c6>;
-	status = "okay";
-};
-
-&snvs_pwrkey {
-	status = "okay";
-};
-
-&uart2 {
-	/* console */
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "okay";
-};
-
-/* SD Card */
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
-	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
-	assigned-clock-rates = <400000000>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	fsl,ext-reset-output;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_eqos: eqosgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
-			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
-			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
-			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
-			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
-			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
-			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
-			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
-			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN			0x1f
-			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT			0x1f
-			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18				0x19
-		>;
-	};
-
-	pinctrl_fec: fecgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC				0x3
-			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO				0x3
-			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x91
-			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x91
-			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x91
-			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x91
-			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x91
-			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x91
-			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x1f
-			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x1f
-			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x1f
-			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x1f
-			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x1f
-			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x1f
-			MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT			0x1f
-			MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN			0x1f
-			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19				0x19
-		>;
-	};
-
-	pinctrl_gpio_led: gpioledgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16				0x19
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2
-			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2
-		>;
-	};
-
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL					0x400001c2
-			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA					0x400001c2
-		>;
-	};
-
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL					0x400001c2
-			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA					0x400001c2
-		>;
-	};
-
-	pinctrl_i2c4: i2c4grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c3
-			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c3
-		>;
-	};
-
-	pinctrl_i2c6: i2c6grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL				0x400001c3
-			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA					0x400001c3
-		>;
-	};
-
-	pinctrl_pmic: pmicirqgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x41
-		>;
-	};
-
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x41
-		>;
-	};
-
-	pinctrl_rtc_int: rtcintgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11				0x140
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x14f
-			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x14f
-		>;
-	};
-
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX				0x49
-			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX				0x49
-		>;
-	};
-
-	pinctrl_uart4: uart4grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX				0x49
-			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX				0x49
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190
-			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0
-			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0
-			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0
-			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0
-			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194
-			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4
-			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4
-			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4
-			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4
-			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196
-			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6
-			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6
-			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6
-			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6
-			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6
-		>;
-	};
-
-	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12				0x1c4
-		>;
-	};
-
-	pinctrl_usdhc3: usdhc3grp {
-		fsl,pins = <
-			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
-			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
-			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
-			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
-			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
-			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
-			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
-			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
-			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
-			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
-			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
-		>;
-	};
-
-	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
-			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
-			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
-			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
-			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
-			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
-			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
-			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
-			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
-			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
-			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
-		>;
-	};
-
-	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
-			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
-			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
-			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
-			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
-			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
-			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
-			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
-			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
-			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
-			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
-		>;
-	};
-
-	pinctrl_wdog: wdoggrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
-		>;
-	};
-};
-
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index d4ac567e7ed..19d12696a1e 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -47,6 +47,8 @@
 #define ELE_ATTEST_REQ (0xDB)
 #define ELE_RELEASE_PATCH_REQ (0xDC)
 #define ELE_OTP_SEQ_SWITH_REQ (0xDD)
+#define ELE_WRITE_SHADOW_REQ (0xF2)
+#define ELE_READ_SHADOW_REQ (0xF3)
 
 /* ELE failure indications */
 #define ELE_ROM_PING_FAILURE_IND (0x0A)
@@ -154,4 +156,6 @@ int ele_release_m33_trout(void);
 int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
 int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
 int ele_start_rng(void);
+int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response);
+int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response);
 #endif
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index ed44df394b1..324e010bb2c 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -345,9 +345,9 @@ int ahab_close(void)
 	u16 lc;
 
 	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in get lifecycle\n");
-		return -EIO;
+		return err;
 	}
 
 	if (lc != 0x20) {
@@ -357,9 +357,9 @@ int ahab_close(void)
 	}
 
 	err = sc_seco_forward_lifecycle(-1, 16);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in forward lifecycle to OEM closed\n");
-		return -EIO;
+		return err;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2ff4ff35e49..37a5473ac7c 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -48,7 +48,7 @@ static char *get_reset_cause(void)
 {
 	sc_pm_reset_reason_t reason;
 
-	if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE)
+	if (sc_pm_reset_reason(-1, &reason))
 		return "Unknown reset";
 
 	switch (reason) {
@@ -160,6 +160,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 	sc_faddr_t tcml_addr;
 	u32 tcml_size = SZ_128K;
 	ulong addr;
+	int ret;
 
 	switch (core_id) {
 	case 0:
@@ -187,10 +188,12 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 	printf("Power on M4 and MU\n");
 
-	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
-		return -EIO;
+	ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON);
+	if (ret)
+		return ret;
 
-	if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+	ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON);
+	if (ret)
 		return -EIO;
 
 	printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
@@ -199,7 +202,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 		memcpy((void *)tcml_addr, (void *)addr, tcml_size);
 
 	printf("Start M4 %u\n", core_id);
-	if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+	ret = sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr);
+	if (ret)
 		return -EIO;
 
 	printf("bootaux complete\n");
@@ -214,6 +218,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 	sc_faddr_t aux_core_ram;
 	u32 size;
 	ulong addr;
+	int ret;
 
 	switch (core_id) {
 	case 0:
@@ -242,20 +247,23 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 	printf("Power on aux core %d\n", core_id);
 
-	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
-		return -EIO;
+	ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON);
+	if (ret)
+		return ret;
 
 	if (mu_rsrc != SC_R_NONE) {
-		if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON);
+		if (ret)
 			return -EIO;
 	}
 
 	if (core_id == 1) {
 		struct power_domain pd;
 
-		if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
+		ret = sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false);
+		if (ret) {
 			printf("Error enable clock\n");
-			return -EIO;
+			return ret;
 		}
 
 		if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) {
@@ -286,8 +294,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 	printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
 
-	if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
-		return -EIO;
+	ret = sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram);
+	if (ret)
+		return ret;
 
 	printf("bootaux complete\n");
 	return 0;
@@ -313,7 +322,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
 		return 0;
 	}
 
-	if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
+	if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode))
 		return 0;
 
 	if (power_mode != SC_PM_PW_MODE_OFF)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d1fdaec7043..9d1fabe91c0 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -197,6 +197,7 @@ config TARGET_IMX8MP_DEBIX_MODEL_A
 	select IMX8MP
 	select IMX8M_LPDDR4
 	select SUPPORT_SPL
+	imply OF_UPSTREAM
 
 config TARGET_IMX8MP_DH_DHCOM_PDK2
 	bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS
index 8f9b5ff2dca..472e908e278 100644
--- a/board/dhelectronics/dh_imx6/MAINTAINERS
+++ b/board/dhelectronics/dh_imx6/MAINTAINERS
@@ -3,6 +3,5 @@ M:	Andreas Geisreiter <ageisreiter@dh-electronics.de>
 M:	Christoph Niedermaier <cniedermaier@dh-electronics.com>
 L:	u-boot@dh-electronics.com
 S:	Maintained
-F:	board/dhelectronics/dh_imx6/
-F:	include/configs/dh_imx6.h
-F:	configs/dh_imx6_defconfig
+N:	imx6.*dh[cs]o
+N:	dh_imx6
diff --git a/board/dhelectronics/dh_imx8mp/MAINTAINERS b/board/dhelectronics/dh_imx8mp/MAINTAINERS
index db69781a852..cf9f77252c9 100644
--- a/board/dhelectronics/dh_imx8mp/MAINTAINERS
+++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS
@@ -2,7 +2,5 @@ DH electronics DHCOM i.MX8M Plus and matching carrier boards
 M:	Marek Vasut <marex@denx.de>
 L:	u-boot@dh-electronics.com
 S:	Maintained
-F:	arch/arm/dts/imx8mp-dhcom*
-F:	board/dhelectronics/dh_imx8mp/
-F:	configs/imx8mp_dhcom*defconfig
-F:	include/configs/imx8mp_dhcom*
+N:	imx8mp.*dh[cs]o
+N:	dh_imx8mp
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index dcc529f9fc2..9f75ab1477f 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-debix-model-a"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-debix-model-a"
 CONFIG_SPL_TEXT_BASE=0x920000
 CONFIG_TARGET_IMX8MP_DEBIX_MODEL_A=y
 CONFIG_SYS_MONITOR_LEN=524288
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 34d91cd6880..1d04090ca00 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -197,6 +197,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
 
 	base = (void *)ANATOP_BASE_ADDR;
 
+	clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
+
 	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index b753419f01b..661f70cf870 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -5,12 +5,12 @@
  *
  */
 
-#include <hang.h>
-#include <malloc.h>
-#include <memalign.h>
 #include <asm/io.h>
-#include <dm.h>
+#include <asm/mach-imx/sys_proto.h>
 #include <asm/mach-imx/ele_api.h>
+#include <dm.h>
+#include <malloc.h>
+#include <memalign.h>
 #include <misc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -205,8 +205,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon
 		return -EINVAL;
 	}
 
-	if ((fuse_id != 1 && fuse_num != 1) ||
-	    (fuse_id == 1 && fuse_num != 4)) {
+	if (is_imx8ulp() && ((fuse_id != 1 && fuse_num != 1) || (fuse_id == 1 && fuse_num != 4))) {
 		printf("Invalid fuse number parameter\n");
 		return -EINVAL;
 	}
@@ -226,7 +225,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon
 		*response = msg.data[0];
 
 	fuse_words[0] = msg.data[1];
-	if (fuse_id == 1) {
+	if (fuse_id == 1 && is_imx8ulp()) {
 		/* OTP_UNIQ_ID */
 		fuse_words[1] = msg.data[2];
 		fuse_words[2] = msg.data[3];
@@ -269,6 +268,72 @@ int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
 	return ret;
 }
 
+int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("ele dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_WRITE_SHADOW_REQ;
+	msg.data[0] = fuse_id;
+	msg.data[1] = fuse_val;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+		       __func__, ret, fuse_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response)
+{
+	struct udevice *dev = gd->arch.ele_dev;
+	int size = sizeof(struct ele_msg);
+	struct ele_msg msg = {};
+	int ret;
+
+	if (!dev) {
+		printf("ele dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	if (!fuse_val) {
+		printf("Invalid parameters for shadow read\n");
+		return -EINVAL;
+	}
+
+	msg.version = ELE_VERSION;
+	msg.tag = ELE_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_READ_SHADOW_REQ;
+	msg.data[0] = fuse_id;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+		       __func__, ret, fuse_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	*fuse_val = msg.data[1];
+
+	return ret;
+}
+
 int ele_release_caam(u32 core_did, u32 *response)
 {
 	struct udevice *dev = gd->arch.ele_dev;
diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index 0cf81f33ba5..cdb85b999db 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -21,25 +21,35 @@ struct imx8ulp_mu {
 
 #define MU_SR_TE0_MASK		BIT(0)
 #define MU_SR_RF0_MASK		BIT(0)
-#define MU_TR_COUNT		8
-#define MU_RR_COUNT		4
 
 void mu_hal_init(ulong base)
 {
 	struct mu_type *mu_base = (struct mu_type *)base;
+	u32 rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+	int i;
 
 	writel(0, &mu_base->tcr);
 	writel(0, &mu_base->rcr);
+
+	while (true) {
+		/* If there is pending RX data, clear them by read them out */
+		if (!(readl(&mu_base->sr) & BIT(6)))
+			return;
+
+		for (i = 0; i < rr_num; i++)
+			readl(&mu_base->rr[i]);
+	}
 }
 
 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
 {
 	struct mu_type *mu_base = (struct mu_type *)base;
 	u32 mask = MU_SR_TE0_MASK << reg_index;
-	u32 val;
+	u32 val, tr_num;
 	int ret;
 
-	assert(reg_index < MU_TR_COUNT);
+	tr_num = readl(&mu_base->par) & 0xFF;
+	assert(reg_index < tr_num);
 
 	debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr));
 
@@ -61,11 +71,12 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
 {
 	struct mu_type *mu_base = (struct mu_type *)base;
 	u32 mask = MU_SR_RF0_MASK << reg_index;
-	u32 val;
+	u32 val, rr_num;
 	int ret;
 	u32 count = 10;
 
-	assert(reg_index < MU_RR_COUNT);
+	rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+	assert(reg_index < rr_num);
 
 	debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr));
 
@@ -96,7 +107,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
 {
 	struct ele_msg *msg = (struct ele_msg *)data;
 	int ret;
-	u8 count = 0;
+	u8 count = 0, rr_num;
 
 	if (!msg)
 		return -EINVAL;
@@ -113,9 +124,11 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
 		return -EINVAL;
 	}
 
+	rr_num = (readl(&base->par) & 0xFF00) >> 8;
+
 	/* Read remaining words */
 	while (count < msg->size) {
-		ret = mu_hal_receivemsg((ulong)base, count % MU_RR_COUNT,
+		ret = mu_hal_receivemsg((ulong)base, count % rr_num,
 					&msg->data[count - 1]);
 		if (ret)
 			return ret;
@@ -129,7 +142,7 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data)
 {
 	struct ele_msg *msg = (struct ele_msg *)data;
 	int ret;
-	u8 count = 0;
+	u8 count = 0, tr_num;
 
 	if (!msg)
 		return -EINVAL;
@@ -144,9 +157,11 @@ static int imx8ulp_mu_write(struct mu_type *base, void *data)
 		return ret;
 	count++;
 
+	tr_num = readl(&base->par) & 0xFF;
+
 	/* Write remaining words */
 	while (count < msg->size) {
-		ret = mu_hal_sendmsg((ulong)base, count % MU_TR_COUNT,
+		ret = mu_hal_sendmsg((ulong)base, count % tr_num,
 				     msg->data[count - 1]);
 		if (ret)
 			return ret;
@@ -229,6 +244,7 @@ static struct misc_ops imx8ulp_mu_ops = {
 static const struct udevice_id imx8ulp_mu_ids[] = {
 	{ .compatible = "fsl,imx8ulp-mu" },
 	{ .compatible = "fsl,imx93-mu-s4" },
+	{ .compatible = "fsl,imx95-mu-ele" },
 	{ }
 };
 
diff --git a/drivers/misc/imx_ele/fuse.c b/drivers/misc/imx_ele/fuse.c
index d12539c8aac..c1e7434dbf3 100644
--- a/drivers/misc/imx_ele/fuse.c
+++ b/drivers/misc/imx_ele/fuse.c
@@ -11,10 +11,10 @@
 #include <env.h>
 #include <asm/mach-imx/ele_api.h>
 #include <asm/global_data.h>
+#include <env.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define FUSE_BANKS	64
 #define WORDS_PER_BANKS 8
 
 struct fsb_map_entry {
@@ -32,6 +32,7 @@ struct ele_map_entry {
 
 #if defined(CONFIG_IMX8ULP)
 #define FSB_OTP_SHADOW	0x800
+#define IS_FSB_ALLOWED (true)
 
 struct fsb_map_entry fsb_mapping_table[] = {
 	{ 3, 8 },
@@ -84,6 +85,8 @@ struct ele_map_entry ele_api_mapping_table[] = {
 };
 #elif defined(CONFIG_ARCH_IMX9)
 #define FSB_OTP_SHADOW	0x8000
+#define IS_FSB_ALLOWED (!IS_ENABLED(CONFIG_SCMI_FIRMWARE) && \
+	!(readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28) & BIT(0)))
 
 struct fsb_map_entry fsb_mapping_table[] = {
 	{ 0, 8 },
@@ -138,8 +141,7 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
 	/* map the fuse from ocotp fuse map to FSB*/
 	for (i = 0; i < size; i++) {
 		if (fsb_mapping_table[i].fuse_bank != -1 &&
-		    fsb_mapping_table[i].fuse_bank == bank &&
-		    fsb_mapping_table[i].fuse_words > word) {
+		    fsb_mapping_table[i].fuse_bank == bank) {
 			break;
 		}
 
@@ -150,8 +152,13 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
 		return -1; /* Failed to find */
 
 	if (fsb_mapping_table[i].redundancy) {
+		if ((fsb_mapping_table[i].fuse_words << 1) <= word)
+			return -2; /* Not valid word */
+
 		*redundancy = true;
 		return (word >> 1) + word_pos;
+	} else if (fsb_mapping_table[i].fuse_words <= word) {
+		return -2; /* Not valid word */
 	}
 
 	*redundancy = false;
@@ -187,24 +194,14 @@ static s32 map_ele_fuse_index(u32 bank, u32 word)
 int fuse_sense(u32 bank, u32 word, u32 *val)
 {
 	s32 word_index;
-	bool redundancy;
 
-	if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+	if (word >= WORDS_PER_BANKS || !val)
 		return -EINVAL;
 
-	word_index = map_fsb_fuse_index(bank, word, &redundancy);
-	if (word_index >= 0) {
-		*val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
-		if (redundancy)
-			*val = (*val >> ((word % 2) * 16)) & 0xFFFF;
-
-		return 0;
-	}
-
 	word_index = map_ele_fuse_index(bank, word);
 	if (word_index >= 0) {
 		u32 data[4];
-		u32 res, size = 4;
+		u32 res = 0, size = 4;
 		int ret;
 
 		/* Only UID return 4 words */
@@ -236,28 +233,29 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 
 	return -ENOENT;
 }
+
 #elif defined(CONFIG_ARCH_IMX9)
 int fuse_sense(u32 bank, u32 word, u32 *val)
 {
 	s32 word_index;
 	bool redundancy;
 
-	if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+	if (word >= WORDS_PER_BANKS || !val)
 		return -EINVAL;
 
-	word_index = map_fsb_fuse_index(bank, word, &redundancy);
-	if (word_index >= 0) {
-		*val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
-		if (redundancy)
-			*val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+	if (!IS_ENABLED(CONFIG_SCMI_FIRMWARE)) {
+		word_index = map_fsb_fuse_index(bank, word, &redundancy);
 
-		return 0;
+		/* ELE read common fuse API supports all FSB fuse. */
+		if (word_index < 0)
+			word_index = map_ele_fuse_index(bank, word);
+	} else {
+		word_index = bank * 8 + word;
 	}
 
-	word_index = map_ele_fuse_index(bank, word);
 	if (word_index >= 0) {
 		u32 data;
-		u32 res, size = 1;
+		u32 res = 0, size = 1;
 		int ret;
 
 		ret = ele_read_common_fuse(word_index, &data, size, &res);
@@ -275,18 +273,62 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 }
 #endif
 
-int fuse_read(u32 bank, u32 word, u32 *val)
+static int fuse_read_default(u32 bank, u32 word, u32 *val)
 {
+	s32 word_index;
+	bool redundancy;
+
+	if (IS_FSB_ALLOWED) {
+		word_index = map_fsb_fuse_index(bank, word, &redundancy);
+		if (word_index >= 0) {
+			*val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
+			if (redundancy)
+				*val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+
+			return 0;
+		}
+	}
+
 	return fuse_sense(bank, word, val);
 }
 
+static int fuse_read_ele_shd(u32 bank, u32 word, u32 *val)
+{
+	u32 res = 0;
+	int ret;
+	struct udevice *dev = gd->arch.ele_dev;
+
+	if (!dev)
+		return -ENODEV;
+
+	ret = ele_read_shadow_fuse((bank * 8 + word), val, &res);
+	if (ret) {
+		printf("ele read shadow fuse failed %d, 0x%x\n", ret, res);
+		return ret;
+	}
+
+	return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	if (word >= WORDS_PER_BANKS || !val)
+		return -EINVAL;
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+	    env_get_yesno("enable_ele_shd") == 1)
+		return fuse_read_ele_shd(bank, word, val);
+	else
+		return fuse_read_default(bank, word, val);
+}
+
 int fuse_prog(u32 bank, u32 word, u32 val)
 {
-	u32 res;
+	u32 res = 0;
 	int ret;
 	bool lock = false;
 
-	if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+	if (word >= WORDS_PER_BANKS || !val)
 		return -EINVAL;
 
 	/* Lock 8ULP ECC fuse word, so second programming will return failure.
@@ -314,6 +356,17 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 
 int fuse_override(u32 bank, u32 word, u32 val)
 {
-	printf("Override fuse to i.MX8ULP in u-boot is forbidden\n");
-	return -EPERM;
+	u32 res = 0;
+	int ret;
+
+	if (word >= WORDS_PER_BANKS || !val)
+		return -EINVAL;
+
+	ret = ele_write_shadow_fuse((bank * 8 + word), val, &res);
+	if (ret) {
+		printf("ahab write shadow fuse failed %d, 0x%x\n", ret, res);
+		return ret;
+	}
+
+	return 0;
 }
diff --git a/tools/binman/etype/nxp_imx8mcst.py b/tools/binman/etype/nxp_imx8mcst.py
index 8221517b0c4..a7d8db4eec4 100644
--- a/tools/binman/etype/nxp_imx8mcst.py
+++ b/tools/binman/etype/nxp_imx8mcst.py
@@ -23,7 +23,9 @@ from u_boot_pylib import tools
 MAGIC_NXP_IMX_IVT = 0x412000d1
 MAGIC_FITIMAGE    = 0xedfe0dd0
 
-csf_config_template = """
+KEY_NAME = 'sha256_4096_65537_v3_usr_crt'
+
+CSF_CONFIG_TEMPLATE = f'''
 [Header]
   Version = 4.3
   Hash Algorithm = sha256
@@ -36,8 +38,11 @@ csf_config_template = """
   File = "SRK_1_2_3_4_table.bin"
   Source index = 0
 
+[Install NOCAK]
+  File = "SRK1_{KEY_NAME}.pem"
+
 [Install CSFK]
-  File = "CSF1_1_sha256_4096_65537_v3_usr_crt.pem"
+  File = "CSF1_1_{KEY_NAME}.pem"
 
 [Authenticate CSF]
 
@@ -48,12 +53,12 @@ csf_config_template = """
 [Install Key]
   Verification index = 0
   Target Index = 2
-  File = "IMG1_1_sha256_4096_65537_v3_usr_crt.pem"
+  File = "IMG1_1_{KEY_NAME}.pem"
 
 [Authenticate Data]
   Verification index = 2
   Blocks = 0x1234 0x78 0xabcd "data.bin"
-"""
+'''
 
 class Entry_nxp_imx8mcst(Entry_mkimage):
     """NXP i.MX8M CST .cfg file generator and cst invoker
@@ -69,9 +74,22 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
     def ReadNode(self):
         super().ReadNode()
         self.loader_address = fdt_util.GetInt(self._node, 'nxp,loader-address')
-        self.srk_table = os.getenv('SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table', 'SRK_1_2_3_4_table.bin'))
-        self.csf_crt = os.getenv('CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt', 'CSF1_1_sha256_4096_65537_v3_usr_crt.pem'))
-        self.img_crt = os.getenv('IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt', 'IMG1_1_sha256_4096_65537_v3_usr_crt.pem'))
+        self.srk_table = os.getenv(
+            'SRK_TABLE', fdt_util.GetString(self._node, 'nxp,srk-table',
+                                            'SRK_1_2_3_4_table.bin'))
+        self.fast_auth = fdt_util.GetBool(self._node, 'nxp,fast-auth')
+        if not self.fast_auth:
+            self.csf_crt = os.getenv(
+                'CSF_KEY', fdt_util.GetString(self._node, 'nxp,csf-crt',
+                                              f'CSF1_1_{KEY_NAME}.pem'))
+            self.img_crt = os.getenv(
+                'IMG_KEY', fdt_util.GetString(self._node, 'nxp,img-crt',
+                                              f'IMG1_1_{KEY_NAME}.pem'))
+        else:
+            self.srk_crt = os.getenv(
+                'SRK_KEY', fdt_util.GetString(self._node, 'nxp,srk-crt',
+                                              f'SRK1_{KEY_NAME}.pem'))
+
         self.unlock = fdt_util.GetBool(self._node, 'nxp,unlock')
         self.ReadEntries()
 
@@ -118,16 +136,26 @@ class Entry_nxp_imx8mcst(Entry_mkimage):
         tools.write_file(output_dname, data)
 
         # Generate CST configuration file used to sign payload
-        cfg_fname = tools.get_output_filename('nxp.csf-config-txt.%s' % uniq)
+        cfg_fname = tools.get_output_filename(f'nxp.csf-config-txt.{uniq}')
         config = configparser.ConfigParser()
         # Do not make key names lowercase
         config.optionxform = str
         # Load configuration template and modify keys of interest
-        config.read_string(csf_config_template)
-        config['Install SRK']['File'] = '"' + self.srk_table + '"'
-        config['Install CSFK']['File'] = '"' + self.csf_crt + '"'
-        config['Install Key']['File'] = '"' + self.img_crt + '"'
-        config['Authenticate Data']['Blocks'] = hex(signbase) + ' 0 ' + hex(len(data)) + ' "' + str(output_dname) + '"'
+        config.read_string(CSF_CONFIG_TEMPLATE)
+        config['Install SRK']['File']  = f'"{self.srk_table}"'
+        if not self.fast_auth:
+            config.remove_section('Install NOCAK')
+            config['Install CSFK']['File'] = f'"{self.csf_crt}"'
+            config['Install Key']['File']  = f'"{self.img_crt}"'
+        else:
+            config.remove_section('Install CSFK')
+            config.remove_section('Install Key')
+            config['Install NOCAK']['File'] = f'"{self.srk_crt}"'
+            config['Authenticate Data']['Verification index'] = '0'
+
+        config['Authenticate Data']['Blocks'] = \
+            f'{signbase:#x} 0 {len(data):#x} "{output_dname}"'
+
         if not self.unlock:
             config.remove_section('Unlock')
         with open(cfg_fname, 'w') as cfgf: