diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com> | 2025-02-18 16:34:50 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:53:41 -0600 |
| commit | 58ef50ff9af1ac64fbfdc05188e8f053bef811c4 (patch) | |
| tree | 99fc160c852eac97a538530149068d9d7ba04d18 | |
| parent | 9e7986e0610d4131592c5885aa669e607298e739 (diff) | |
drivers: clk: agilex5: Set PLL to asynchronous mode
PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
| -rw-r--r-- | drivers/clk/altera/clk-agilex5.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index a284b562486..fb1e72ffc5c 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -73,15 +73,6 @@ static const struct { u32 mask; } membus_pll[] = { { - MEMBUS_CLKSLICE_REG, - /* - * BIT[7:7] - * Enable source synchronous mode - */ - BIT(7), - BIT(7) - }, - { MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, /* * BIT[0:0] |