diff options
| author | Michal Simek <michal.simek@amd.com> | 2025-07-22 13:03:45 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2025-08-14 14:32:00 +0800 |
| commit | 5fe8b532092ff7e7d822db7ef03b501547d22e56 (patch) | |
| tree | 1efd916550ba44d2aabaa41022dc4d2508b4d434 | |
| parent | 441ac0814216a0b29df675aec03c6de5b45ffbd6 (diff) | |
xilinx: mbv: Fix dt properties in interrupt controller node
Properties didn't match dt binding that's why should be fixed.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/dts/xilinx-mbv32.dts | 3 | ||||
| -rw-r--r-- | arch/riscv/dts/xilinx-mbv64.dts | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 96e42806244..b426510f343 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -71,7 +71,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts index 5a989c1697e..3762def29f9 100644 --- a/arch/riscv/dts/xilinx-mbv64.dts +++ b/arch/riscv/dts/xilinx-mbv64.dts @@ -71,7 +71,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { |