diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-03-13 11:02:35 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-03-19 10:59:24 +0200 |
| commit | 65e4869a10dc7484924172149e9d7757a9ae5702 (patch) | |
| tree | 6f34d48db6ddd50f68b9da0fabbdeccbf6a8e838 | |
| parent | 59bc30822177de6b79851b8bc1da4b8283273509 (diff) | |
pinctrl: tegra: adjust pin state lists
Modify the pin state lists for lock, io-reset, rcv-sel, and e-io-hv
properties by repositioning the default value to the end. This change
addresses conflicts with device tree representations of TEGRA_PIN_DISABLE
and TEGRA_PIN_ENABLE.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/pinmux.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 4b6e8419504..9a5cc93884c 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -34,41 +34,41 @@ enum pmux_pin_io { #ifdef TEGRA_PMX_PINS_HAVE_LOCK enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_DISABLE = 0, PMUX_PIN_LOCK_ENABLE, + PMUX_PIN_LOCK_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_OD enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_DISABLE = 0, PMUX_PIN_OD_ENABLE, + PMUX_PIN_OD_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_DISABLE = 0, PMUX_PIN_IO_RESET_ENABLE, + PMUX_PIN_IO_RESET_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_NORMAL = 0, PMUX_PIN_RCV_SEL_HIGH, + PMUX_PIN_RCV_SEL_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV enum pmux_pin_e_io_hv { - PMUX_PIN_E_IO_HV_DEFAULT = 0, - PMUX_PIN_E_IO_HV_NORMAL, + PMUX_PIN_E_IO_HV_NORMAL = 0, PMUX_PIN_E_IO_HV_HIGH, + PMUX_PIN_E_IO_HV_DEFAULT, }; #endif |