diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-08-03 18:24:32 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-08-08 22:19:23 +0800 |
| commit | 677147c167ecbf4ac220a099b849cc7a5a03fec4 (patch) | |
| tree | 467caca4f56bfa3f0e429a41e1250cc9a049efb9 | |
| parent | 60a377db98734e81143df79b54a55afd6ecc4c74 (diff) | |
arm: socfpga: Update Agilex SPL data save and restore implementation
Enable backup for data section to support warm reset in Agilex SPL as
no SPL image would be reloaded in warm reset.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
| -rw-r--r-- | arch/arm/mach-socfpga/spl_agilex.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index faba0433838..698e76f45b2 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -23,11 +24,29 @@ DECLARE_GLOBAL_DATA_PTR; +u32 reset_flag(void) +{ + /* Check rstmgr.stat for warm reset status */ + u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); + + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK; + + if (status & warm_reset_mask) + return 0; + + return 1; +} + void board_init_f(ulong dummy) { int ret; struct udevice *dev; +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) + spl_save_restore_data(); +#endif + ret = spl_early_init(); if (ret) hang(); |