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authorHeiko Thiery <heiko.thiery@gmail.com>2021-09-09 14:59:18 +0200
committerStefano Babic <sbabic@denx.de>2022-02-05 13:38:38 +0100
commit6ff55bcd07aa911d7e2ba514fe9b92c969805763 (patch)
tree54ef8c763801b149850af6948214f096bfc66cb5
parent0c141103b4601cf0957122255f5b284184be9117 (diff)
arm: imx: imx8mq: add support to get values for more clocks
Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK, MXC_UART_CLK and MXC_QSPI_CLK. At least for the I2C clock the missing support leads to a wrong configured I2C frequency. The expected value is 100kHz but the resulting value is about 1MHz. Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mq.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 60e2218a3cc..9db62b944e4 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -359,10 +359,18 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
case MXC_ESDHC_CLK:
return get_root_clk(USDHC1_CLK_ROOT);
case MXC_ESDHC2_CLK:
return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_QSPI_CLK:
+ return get_root_clk(QSPI_CLK_ROOT);
default:
return get_root_clk(clk);
}