diff options
| author | Quentin Schulz <quentin.schulz@cherry.de> | 2024-06-06 10:45:36 +0200 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2024-06-14 17:11:29 +0800 |
| commit | 724d3c686c57b3ce50a39dceb3f3f1ebc9d3e32c (patch) | |
| tree | e147673c2ac5985f1a340eef0e2bee2d7e597cc5 | |
| parent | 2ce40542e0ebc9b782954ae6df3a23885ff60cf1 (diff) | |
rockchip: ringneck-px30: fix TPL_MAX_SIZE
Ringneck was mistakenly set to allow up to 128KiB for the TPL code size
while PX30 SoC only has 16KiB of SRAM.
Therefore, let's use the default value of TPL_MAX_SIZE from the SoC
(which is 10KiB) so that the max code size is actually checked and
useful.
Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
| -rw-r--r-- | configs/ringneck-px30_defconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index a22d25e0089..9965e55d611 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_DEBUG_UART_BASE=0xFF030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y |