diff options
| author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-10-11 16:38:25 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-21 15:27:33 -0600 |
| commit | 73ab8196886c145983d5ff5514c179487df0c6e1 (patch) | |
| tree | 3cc8dfda8b31c962a6b7419833e66e4dd5dd8bb5 | |
| parent | ef6f4f8e3c0de80f5f6dc4a77d6b18078e6fd2df (diff) | |
usb: dwc3: fix dcache flush range calculation
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with CACHELINE_SIZE.
This causes operation failures Qualcomm platforms.
Take in account the alignment and size of the buffer and also
flush the previous and last cacheline.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
| -rw-r--r-- | drivers/usb/dwc3/io.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..0ede323671b 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE); + + flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */ |