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authorShmuel Leib Melamud <smelamud@redhat.com>2025-06-11 03:25:51 +0300
committerMarek Vasut <marek.vasut+renesas@mailbox.org>2025-06-18 15:08:52 +0200
commit77700bcc1dc50651567e0835dbcf1710cdb108fc (patch)
tree57d70ea0e26d3dd681958969eaecbcdda068a30e
parentdd8f57ed2f0be7dd6c8adc8e1823937f7006950c (diff)
clk: renesas: Handle CLK_TYPE_GEN4_MDSEL in gen3_clk_get_rate64()
Add support of CLK_TYPE_GEN4_MDSEL clock type to gen3_clk_get_rate64() function. In particular, this type of clock is used by Renesas R-Car Gen4 watchdog. It operates similarly to CLK_TYPE_GEN3_MDSEL clock. Signed-off-by: Shmuel Leib Melamud <smelamud@redhat.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Stefan Roese <sr@denx.de>
-rw-r--r--drivers/clk/renesas/clk-rcar-gen3.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 375cc4a4930..5745acf4023 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -68,7 +68,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
if (ret)
return ret;
- if (core->type == CLK_TYPE_GEN3_MDSEL) {
+ if (core->type == CLK_TYPE_GEN3_MDSEL || core->type == CLK_TYPE_GEN4_MDSEL) {
shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
parent->dev = clk->dev;
parent->id = core->parent >> shift;
@@ -318,6 +318,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
"FIXED");
case CLK_TYPE_GEN3_MDSEL:
+ fallthrough;
+ case CLK_TYPE_GEN4_MDSEL:
shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
div = (core->div >> shift) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div;