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authorMuhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com>2025-03-13 19:19:52 -0700
committerMichal Simek <michal.simek@amd.com>2025-04-16 13:42:06 +0200
commit82dd190807e42f25d0bd2f5c20b5cfb90d353040 (patch)
tree5c01dbc6f0173713c12d8209fde68d49bedad9d8
parenta93cc9b9c56870fe134fe2006a1f46d9557ec780 (diff)
drivers: fpga: Add FPGA configuration during bootm for Intel SOCFPGA
Enabling the capability to automatically perform FPGA configuration when booting Linux FIT image via bootm command. The FPGA configuration bitstream shall be packed within the FIT image. The FPGA data (full or partial) is checked by the SDM hardware, for Intel SDM Mailbox based devices. Hence always return full bitstream. Second function is to enable the HPS to FPGA bridges when FPGA load is completed successfully. This is to ensure the FPGA is accessible by the HPS. Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com> Link: https://lore.kernel.org/r/20250314021953.18379-2-muhammad.hazim.izzat.zamri@altera.com Signed-off-by: Michal Simek <michal.simek@amd.com>
-rw-r--r--drivers/fpga/altera.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index ae06f0123a0..136ccfc2de4 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -12,6 +12,10 @@
/*
* Altera FPGA support
*/
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/misc.h>
+#endif
#include <errno.h>
#include <ACEX1K.h>
#include <log.h>
@@ -47,6 +51,42 @@ static const struct altera_fpga {
#endif
};
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+int fpga_is_partial_data(int devnum, size_t img_len)
+{
+ /*
+ * The FPGA data (full or partial) is checked by
+ * the SDM hardware, for Intel SDM Mailbox based
+ * devices. Hence always return full bitstream.
+ *
+ * For Cyclone V and Arria 10 family, the bitstream
+ * type parameter is not handled by the driver.
+ */
+ return 0;
+}
+
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype)
+{
+ int ret_val;
+
+ ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype);
+
+ /*
+ * Enable the HPS to FPGA bridges when FPGA load is completed
+ * successfully. This is to ensure the FPGA is accessible
+ * by the HPS.
+ */
+ if (!ret_val) {
+ printf("Enable FPGA bridges\n");
+ do_bridge_reset(1, ~0);
+ }
+
+ return ret_val;
+}
+#endif
+
static int altera_validate(Altera_desc *desc, const char *fn)
{
if (!desc) {