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| author | Simon Glass <sjg@chromium.org> | 2024-09-29 19:49:43 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-11 11:44:47 -0600 |
| commit | 8651eb1f253cd96491a8340844e195769cbbd6eb (patch) | |
| tree | 8f92e41dff2626c0d124650f68cd11214260af74 | |
| parent | e16bfd9e586a4114920e463f7af4fb87be6d3bc3 (diff) | |
README: Drop SoC-specific comment about SPL
This should not be in the generic README file, so drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | README | 10 |
1 files changed, 1 insertions, 9 deletions
@@ -213,15 +213,7 @@ board_init_r(): there. SPL-specific notes: - - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and - CONFIG_SYS_FSL_HAS_CCI400 - - Defined For SoC that has cache coherent interconnect - CCN-400 - - CONFIG_SYS_FSL_HAS_CCN504 - - Defined for SoC that has cache coherent interconnect CCN-504 + - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined The following options need to be configured: |