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authorMarek Vasut <marex@denx.de>2020-05-26 04:30:20 +0200
committerPatrick Delaunay <patrick.delaunay@st.com>2020-05-28 08:52:04 +0200
commit8b4101d0f9a48a8491043049ed6c7de7d75c63ee (patch)
treea4b130b575ca90983c73f096e05fe70bcedc258d
parent3f662a67966daacb5e838e64041181e88f9651ab (diff)
ARM: stm32: Hog GPIO PF7 high on DHCOR to unlock SPI NOR nWP
The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line high by default to clear SPI NOR WP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
-rw-r--r--arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi9
-rw-r--r--configs/stm32mp15_dhcor_basic_defconfig1
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index ef730a83220..bd4c2adc358 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -21,6 +21,15 @@
};
};
+&gpiof {
+ snor-nwp {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ line-name = "spi-nor-nwp";
+ };
+};
+
&i2c4 {
u-boot,dm-pre-reloc;
};
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 7163d0ad1b0..249646c4494 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -71,6 +71,7 @@ CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_VIRT=y
+CONFIG_GPIO_HOG=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_DM_I2C=y