riscv: dts: jh7110: remove redundant parent nodes

- use upstream alias name for cpu and timer nodes
- remove bootph-pre-ram hint from parent nodes
- drop S7 cpu core "okay" status

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

1 files changed, 28 insertions, 44 deletions

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index a9e318c4a31..b4b656b444b 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -6,46 +6,6 @@
 #include <dt-bindings/reset/starfive,jh7110-crg.h>
 
 / {
-	cpus: cpus {
-		bootph-pre-ram;
-
-		S7_0: cpu@0 {
-			bootph-pre-ram;
-			status = "okay";
-			cpu0_intc: interrupt-controller {
-				bootph-pre-ram;
-			};
-		};
-
-		U74_1: cpu@1 {
-			bootph-pre-ram;
-			cpu1_intc: interrupt-controller {
-				bootph-pre-ram;
-			};
-		};
-
-		U74_2: cpu@2 {
-			bootph-pre-ram;
-			cpu2_intc: interrupt-controller {
-				bootph-pre-ram;
-			};
-		};
-
-		U74_3: cpu@3 {
-			bootph-pre-ram;
-			cpu3_intc: interrupt-controller {
-				bootph-pre-ram;
-			};
-		};
-
-		U74_4: cpu@4 {
-			bootph-pre-ram;
-			cpu4_intc: interrupt-controller {
-				bootph-pre-ram;
-			};
-		};
-	};
-
 	timer {
 		compatible = "riscv,timer";
 		interrupts-extended = <&cpu0_intc 5>,
@@ -58,10 +18,6 @@
 	soc {
 		bootph-pre-ram;
 
-		clint: timer@2000000 {
-			bootph-pre-ram;
-		};
-
 		dmc: dmc@15700000 {
 			bootph-pre-ram;
 			compatible = "starfive,jh7110-dmc";
@@ -78,6 +34,34 @@
 	};
 };
 
+&clint {
+	bootph-pre-ram;
+};
+
+&cpu0_intc {
+	bootph-pre-ram;
+};
+
+&cpu1_intc {
+	bootph-pre-ram;
+};
+
+&cpu2_intc {
+	bootph-pre-ram;
+};
+
+&cpu3_intc {
+	bootph-pre-ram;
+};
+
+&cpu4_intc {
+	bootph-pre-ram;
+};
+
+&cpus {
+	bootph-pre-ram;
+};
+
 &osc {
 	bootph-pre-ram;
 };