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authorPeng Fan <peng.fan@nxp.com>2024-04-12 22:24:54 +0800
committerFabio Estevam <festevam@gmail.com>2024-04-15 08:09:41 -0300
commit8ecb0931940cc19728d686b9dba06585f4d93709 (patch)
tree4ee41463db270918cd03324d2ed14cc1c30b0966
parent9422e1c44167e46bdf017736c96ef33ec28c9500 (diff)
clk: imx93: fix anatop base
The PLL clk needs use anatop base, otherwise wrong PLL address will be used. Fixes: 9c153e46661b ("clk: imx: add i.MX93 CCF driver") Signed-off-by: Peng Fan <peng.fan@nxp.com>
-rw-r--r--drivers/clk/imx/clk-imx93.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index ce10d795316..f0cb797d975 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -289,7 +289,7 @@ static int imx93_clk_probe(struct udevice *dev)
clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
- base = (void *)ANATOP_BASE_ADDR;
+ anatop_base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX93_CLK_ARM_PLL,
imx_clk_fracn_gppll_integer("arm_pll", "clock-osc-24m",