diff options
| author | Tingting Meng <tingting.meng@altera.com> | 2025-08-03 18:25:01 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-08-08 22:20:55 +0800 |
| commit | 8eecbaf957191b159176e92175121db907c480b2 (patch) | |
| tree | 26cc76f4bd48021be44ab80fdd4c266232d62872 | |
| parent | 2f429d2eb4bb22587dba7546741142e413eb9204 (diff) | |
configs: Add defconfig for Agilex7 M-series
Add defconfig for Agilex7 M-series.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
| -rw-r--r-- | configs/socfpga_agilex7m_defconfig | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/configs/socfpga_agilex7m_defconfig b/configs/socfpga_agilex7m_defconfig new file mode 100644 index 00000000000..0a8c58234b9 --- /dev/null +++ b/configs/socfpga_agilex7m_defconfig @@ -0,0 +1,19 @@ +#include <configs/socfpga_agilex_defconfig> + +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +# CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK is not set +# CONFIG_IDENT_STRING is not set +CONFIG_SPL_BSS_START_ADDR=0x1ff00000 +CONFIG_TARGET_SOCFPGA_AGILEX7M_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex7m" +# CONFIG_QSPI_BOOT is not set +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x1fa00000 +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX7M # " +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),-(root)" +# CONFIG_ENV_IS_IN_UBI is not set +# CONFIG_ENV_UBI_PART is not set +# CONFIG_ENV_UBI_VOLUME is not set +# CONFIG_USE_BOOTFILE is not set +# CONFIG_DESIGNWARE_SPI is not set |